• Geotechnical Engineering
• /
• v.11 no.3
• /
• pp.91-112
• /
• 1995

Drilled shafts are used increasingly as the foundations for many types of structures. However, very little knowledge of drilled shaft behavior under inclined load is available. In this study, a systematic experimental testing program was conducted to understand the undrained behavior of drilled shaft foundations under inclined loads. A semi-theoretical method of predicting the inclined capacity was developed through a parametric study of the variables such as shaft geometry and load inclination. Test parameters were chosen to be representative of those most frequently used in the electric utility industry. Short, rigid shafts with varying depth/diameter(D/B) ratios were addressed, and loading modes were investigated that includes exial uplift, inclined uplift, and inclined compression loads. Capacities were evaluated using the structural interaction formula and an equation developed from this experimental study. This new equation models the laboratory data well and is applicable for the limites field data.

• Journal of IKEEE
• /
• v.23 no.3
• /
• pp.832-838
• /
• 2019

In this paper, 4H-SiC MOSFET, the next generation power semiconductor device, was studied. In particular, Semi-SJ MOSFET structures with improved electrical characteristics than conventional DMOSFET structures were proposed in the class of 3300V, and static characteristics of conventional and proposed structures were compared and analyzed through TCAD simulations. Semi-SuperJunction MOSFET structure is partly structure that introduces SuperJunction, improves Electric field distribution through the two-dimensional depletion effect, and increases breakdown voltage. Benefit from the improvement of breakdown voltage, which can improve the on resistance as high doping is possible. The proposed structure has a slight reduction in breakdown voltage, but has an 80% decrease in on resistance compared to the conventional DMOSFET structure, and a 44% decrease in on resistance compared to the Current Spreading Layer(CSL) structure that improves the conventional DMOSFET structure.

• Journal of IKEEE
• /
• v.25 no.1
• /
• pp.1-9
• /
• 2021

In this paper, a 4H-SiC UMOSFET was studied which is suitable for high voltage and high current applications. In general, SiO2 is a material most commonly used as a gate dielectric material in SiC MOSFETs. However, since the dielectric constant value is 2.5 times lower than 4H-SiC, it suffers a high electric field and has poor characteristics in the SiO2/SiC junction. Therefore, the static characteristics of a device with high-k material as a gate dielectric and a device with SiO2 were compared using TCAD simulation. The results show BV decreased, VTH decreased, gm increased, and Ron decreased. Especially when the temperature is 300K, the Ron of Al2O3 and HfO2 decreases by 66.29% and 69.49%. and at 600K, Ron decreases by 39.71% and 49.88%, respectively. Thus, Al2O3 and HfO2 are suitable as gate dielectric materials for high voltage SiC MOSFET.

• Journal of the Korean Magnetics Society
• /
• v.15 no.5
• /
• pp.270-275
• /
• 2005

Dust cores (compressed powder cores) of $Fe-6.0wt\%Si$ alloy with a size of $35\~180\;{\mu}m$ in diameter have been prepared by phosphate coatings and annealings at $600\~900^{\circ}C$ for 1 h in nitrogen atmosphere. Further the magnetic and mechanical properties of the powder cores were investigated. As a general trends, the compressive strength and core loss decreased with the increase in annealing temperature. When annealed at $800^{\circ}C$, the compressive strength was 15 kgf, the permeability and quality factor were 74 and 26, respectively. Moreover the core loss at 50 kHz and 0.1 T induction was $750\;mW/cm^3$, and the percent permeability under the static field of 50 Oe was estimated to be about 78. In addition, the cut-off frequency in the cure representing the frequency dependence of effective permeability was measured to be around 200 kHz. These properties of the $Fe-6.0wt\%Si$ alloy dust cores could be considered to be due to the good insulation effect of iron-phosphate coats, the decrease in magnetocrystalline anisotropy and saturation magnetostriction and the increase in electric resistivity.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2009.11a
• /
• pp.55-55
• /
• 2009

Silicon Carbide (SiC) is a material with a wide bandgap (3.26eV), a high critical electric field (~2.3MV/cm), a and a high bulk electron mobility (${\sim}900cm^2/Vs$). These electronic properties allow high breakdown voltage, high frequency, and high temperature operation compared to Silicon devices. Although various SiC DMOSFET structures have been reported so far for optimizing performances. the effect of channel dimension on the switching performance of SiC DMOSFETs has not been extensively examined. In this paper, we report the effect of the interface states ($Q_s$) on the transient characteristics of SiC DMOSFETs. The key design parameters for SiC DMOSFETs have been optimized and a physics-based two-dimensional (2-D) mixed device and circuit simulator by Silvaco Inc. has been used to understand the relationship with the switching characteristics. To investigate transient characteristic of the device, mixed-mode simulation has been performed, where the solution of the basic transport equations for the 2-D device structures is directly embedded into the solution procedure for the circuit equations. The result is a low-loss transient characteristic at low $Q_s$. Based on the simulation results, the DMOSFETs exhibit the turn-on time of 10ns at short channel and 9ns at without the interface charges. By reducing $SiO_2/SiC$ interface charge, power losses and switching time also decreases, primarily due to the lowered channel mobilities. As high density interface states can result in increased carrier trapping, or recombination centers or scattering sites. Therefore, the quality of $SiO_2/SiC$ interfaces is important for both static and transient properties of SiC MOSFET devices.