• Title/Summary/Keyword: Standard cell library

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Design of a Blind DFE Equalizer for high-speed data communication (고속 데이터 통신을 위한 Blind DFE Equalizer의 설계)

  • 박원흠;선우명훈
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.27 no.7C
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    • pp.704-711
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    • 2002
  • This paper proposes a DFE (Decision Feedback Equalizer) equalizer ASIC using the Multi-Modulus Algorithm (MMA) for cable modem applications. We believe that it is the first effort to combine the DFE structure and the MMA algorithm. The proposed equalizer has been designed for 64/256 QAM modems. The existing MMA equalizer uses two transversal filters and updates two tap weights while the proposed equalizer uses two DFE filter banks to improve the channel adaptive performance and to reduce the number of taps and updates only one tap weights. We have used the 0.35 $\mu\textrm{m}$ standard cell library. The implemented equalizer ASIC operates at 8 MHz and provides 64 Mbps which is higher than existing equalizers. The total number of gates are about 160,000.

Design of Self-Timed Standard Library and Interface Circuit

  • Jung, Hwi-Sung;Lee, Moon-Key
    • Proceedings of the IEEK Conference
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    • 2000.07a
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    • pp.379-382
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    • 2000
  • We designed a self-timed interface circuit for efficient communication in IP (Intellectual Property)-based system with high-speed self-timed FIFO and a set of self-timed event logic library with 0.25um CMOS technology. Optimized self-timed standard cell layouts and Verilog models are generated for top-down design methodology. A method for mitigating a design bottleneck when it comes to tolerate clock skew is described. With clock control method and FIFO, we implemented high-speed 32bit-interface chip for self-timed system, which generated maximum system clock is 2.2GHz. The size of the core is about 1.1mm x 1.1mm.

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Security Enhancing of Authentication Protocol for Hash Based RFID Tag (해쉬 기반 RFID 태그를 위한 인증 프로토콜의 보안성 향상)

  • Jeon, Jin-Oh;Kang, Min-Sup
    • Journal of Internet Computing and Services
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    • v.11 no.4
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    • pp.23-32
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    • 2010
  • In this paper, we first propose the security enhancing of authentication protocol for Hash based RFID tag, and then a digital Codec for RFID tag is designed based on the proposed authentication protocol. The protocol is based on a three-way challenge response authentication protocol between the tags and a back-end server. In order to realize a secure cryptographic authentication mechanism, we modify three types of the protocol packets which defined in the ISO/IEC 18000-3 standard. Thus active attacks such as the Man-in-the-middle and Replay attacks can be easily protected. In order to verify effectiveness of the proposed protocol, a digital Codec for RFID tag is designed using Verilog HDL, and also synthesized using Synopsys Design Compiler with Hynix $0.25\;{\mu}m$ standard-cell library. Through security analysis and comparison result, we will show that the proposed scheme has better performance in user data confidentiality, tag anonymity, Man-in-the-middle attack prevention, replay attack, forgery resistance and location tracking.

Design of a systolic radix-4 finite-field multiplier for the elliptic curve cryptosystem (타원곡선 암호를 위한 시스톨릭 Radix-4 유한체 곱셈기의 설계)

  • Kim, Ju-Young;Park, Tae-Geun
    • Proceedings of the IEEK Conference
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    • 2005.11a
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    • pp.695-698
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    • 2005
  • The finite-field multiplication can be applied to the wide range of applications, such as signal processing on communication, cryptography, etc. However, an efficient algorithm and the hardware design are required since the finite-field multiplication takes much time to compute. In this paper, we propose a radix-4 systolic multiplier on $GF(2^m)$ with comparative area and performance. The algorithm of the proposed standard-basis multiplier is mathematically developed to map on low-cost systolic cell, so that the proposed systolic architecture is suitable for VLSI design. Compared to the bit-serial and digit-serial multipliers, the proposed multiplier shows relatively better performance with low cost. We design and synthesis $GF(2^{193})$ finite-field multiplier using Hynix $0.35{\mu}m$ standard cell library and the maximum clock frequency is 400MHz.

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An Efficient Delay Calculation Tool for Timing Analysis (타이밍 분석을 위한 효율적인 시간 지연 계산 도구)

  • Kim, Joon-Hee;Kim, Boo-Sung;Kal, Won-Koang;Maeng, Tae-Ho;Baek, Jong-Humn;Kim, Seok-Yoon
    • Proceedings of the KIEE Conference
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    • 1998.11b
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    • pp.612-614
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    • 1998
  • As chip feature size decrease, interconnect delay gains more importance. A accurate timing analysis required to estimate interconnect delay as well as cell delay. In this paper, we present a timing-level delay calculation tool of which the accuracy is bounded within 10% of SPICE results. This delay calculation tool generates delay values in SDF(Standard Delay Format) for parasitic data extracted in SPEF(Standard Parasitic Exchange Format). The efficiency of the tool is easily seen because it uses AWE(Asymptotic Waveform Evaluation) algorithm for interconnect delay calculation, and precharacterized library and effective capacitance model for cell delay calculation.

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Design of Digital Codec for EPC RFID Protocols Generation 2 Class 1 Codec (EPC RFID 프로토콜 제너레이션 2 클래스 1 태그 디지털 코덱 설계)

  • Lee Yong-Joo;Jo Jung-Hyeon;Kim Hyung-Kyu;Kim Sag-Hoon;Lee Yong-Surk
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.31 no.3A
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    • pp.360-367
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    • 2006
  • In this paper, we designed a digital codec of an RFID tag for EPC global generation 2 class 1. There are a large number of studies on RRD standard and anti-collision algorithm but few studies on the design of digital parts of the RFID tag itself. For this reason, we studied and designed the digital codec hardware for EPC global generation 2 class 1 tag. The purpose of this paper is not to improve former studies but to present the hardware architecture, an estimation of hardware size and power consumption of digital part of the RFID tag. Results are synthesized using Synopsys with a 0.35um standard cell library. The hardware size is estimated to be 111640 equivalent inverters and dynamic power is estimated to be 10.4uW. It can be improved through full-custom design, but we designed using a standard cell library because it is faster and more efficient in the verification and the estimation of the design.

VTR Servo Motor 제어용 회로의 IC화

  • 이광엽;임충빈;이문기;김용석;홍현석;김용환;김영웅
    • Proceedings of the Korean Institute of Communication Sciences Conference
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    • 1986.10a
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    • pp.91-94
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    • 1986
  • In this paper, a servo motor control IC for VTR is developed using standard cell library. All the cells are designed by single metal and the 3um design rule. A desinged circuit consists of circuits which generates a switching pulse and a control reference signal in VTR. The operation of VTR chip is verified by COSMOS simulator. Finally, layout is drawn by YOSELA.

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Design of a Deblocking Filter Circuit for MPEG-4 CODEC (MPEG-4 CODEC용 디블로킹 필터 회로 설계)

  • 김승호;조경순
    • Proceedings of the IEEK Conference
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    • 2003.07b
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    • pp.831-834
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    • 2003
  • 본 논문에서 기술하고 있는 디블로킹 필터는 ISO/1EC 14496-2 의 디블로킹 필터링 알고리즘[1][2]을 기반으로 한다. 한 개의 레지스터 뱅크를 이용한 효율적인 데이터 스케줄링을 통해 면적과 전력 측면에서 디블로킹 필터를 사용함으로써 생기는 오버헤드를 최소화 시켰으며, CIF 급 영상을 27MHz 동작주파수에서 실시간으로 처리할 수 있도록 설계 하였다. 0.25㎛ Standard Cell Library 로 합성한 결과 총 9800 게이트로 구성 되었으며, 외부 메모리의 도움 없이 동작 시키기 위해 4.4KByte의 버퍼가 사용되었다.

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Development of a Rectangle-based Layout Object Extraction Algorithm (직사각형을 기반으로 하는 레이아웃 개체추출 알고리즘)

  • 최용석;천익재;김보관
    • Proceedings of the IEEK Conference
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    • 2001.06b
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    • pp.113-116
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    • 2001
  • In this paper we present a new hierarchical layout object extraction algorithm, which is based on rectangles rather than edges. The original layout data is modeled as instances connected by wires. Each polygon shape is divided into a set of rectangles and the instances and wires are extracted and recognized from those rectangles together with their connection and size information. We have applied the algorithm to actual layouts. Experiments on several standard cell library demonstrate the effectiveness of the algorithm.

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Design of Serial ATA Transport layer (직렬 ATA 전송층 설계)

  • 조은숙;박상봉;허정화
    • Proceedings of the IEEK Conference
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    • 2003.11c
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    • pp.365-368
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    • 2003
  • In this Paper, we report a design of Serial ATA Transpor layer. The functionalities of the Serial ATA transport layer are first described on RTL via verilog. The compiled code are then fed to a synthesizer synopsys to get the actual hardware from 0.35$\mu\textrm{m}$ SAMSUNG standard cell library. The designed functionalities of this chip will be verified using test bold with FPGA equipment and ATS2 digital test equipment.

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