• BMB Reports
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• v.45 no.8
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• pp.482-487
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• 2012

To identify the novel inhibitors of endoplasmic reticulum stress-induced cell death, we performed a high throughput assay with a chemical library containing a total of 3,280 bioactive small molecules. Cyclosporine A and bromocriptine were identified as potent inhibitors of thapsigargiin-induced cell death (cut-off at $4{\sigma}$ standard score). However, U74389G, the potent inhibitor of lipid peroxidation had lower activity in inhibiting cell death. The inhibition effect of cyclosporine A and bromocriptine was specific for only thapsigargin-induced cell death. The mechanism of inhibition by these compounds was identified as modification of the expression of glucose regulated protein-78 (GRP-78/Bip) and inhibition of phosphorylation of p38 mitogen activated protein kinase (MAPK). However, these compounds did not inhibit the same events triggered by tunicamycin, which was in agreement with the cell survival data. We suggest that the induction of protective unfolded protein response by these compounds confers resistance to cell death. In summary, we identified compounds that may provide insights on cell death mechanisms stimulated by ER stress.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.12C
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• pp.1182-1191
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• 2003

In this paper, we propose a new hardware architecture for integer transform, quantizer, inverse quantizer, and inverse integer transform of a new video coding standard H.264/JVT. We describe the algorithm and derive hardware architecture emphasizing the importance of area for low cost and low power consumption. The proposed architecture has been verified by PCI-interfaced emulation board using APEX-II Alters FPGA and also by ASIC synthesis using Samsung 0.18 um CMOS cell library. The ASIC synthesis result shows that the proposed hardware can operate at 100 MHz, processing more than 1,300 QCIF video frames per second. The hardware is going to be used as a core module when implementing a complete H.264 video encoder/decoder ASIC for real-time multimedia application.

• Molecular & Cellular Toxicology
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• v.2 no.3
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• pp.170-175
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• 2006

The extensive isolation of genes responsive to stressful conditions from a soft coral Scleronephthya gracillimum was described. Soft coral colonies were exposed to thermal and chemical stressors to induce the expression of stress related genes. Differentially expressed genes by natural or anthropogenic stressors were identified by construction of standard and stress exposed-paired subtractive cDNA library. Thirty-two and thirty-seven kinds of candidate genes were identified from thermal or benzo[a]pyrene stress exposed group, respectively, which are associated with cell cycle, cell signaling, transcription, translation, protein metabolism, and other cellular functions. The expected function of each gene was described. The isolated and identified differentially expressed genes have a great potential to identify environmental stressors in global environmental changes and could act as molecular biomarkers for biological responses against environmental changes. Finally, it may open a new paradigm on soft coral health assessment.

• Proceedings of the IEEK Conference
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• 2000.06b
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• pp.221-225
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• 2000

We designed asynchronous event logic library with 0.25$\mu\textrm{m}$ CMOS technology and interface chip for heterogeneous system with high-speed asynchronous FIFO operating at 1.6㎓. Optimized asynchronous standard cell layouts and Verilog models are designed for top-down design methodology. A method for mitigating a design bottleneck when it comes to tolerate clock skew is described. This communication scheme using clock control circuits, which is used for the free of synchronization failures, is analyzed and implemented. With clock control circuit and FIFO, high-speed communication between synchronous modules operating at different clock frequencies or with asynchronous modules is performed. The core size of implemented high-speed 32bit-interface chip for heterogeneous system is about 1.1mm ${\times}$ 1.1mm.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.12
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• pp.93-101
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• 2007

Small area and low power implementation are important requirements for various multimedia processing hardware, especially for mobile environment. This paper presents a hardware architecture of H.264/AVC Intra Prediction module aiming on small area and low power. A single arithmetic unit was shared and processed sequentially for all mode decisions and computations to predict an image frame. As a result, we could get smaller area and smaller memory size compared to other existing implementations. The proposed architecture was verified using the Altera Excalibur device, and the implemented hardware has been described in Verilog-HDL and synthesized on Samsung STD130 0.18um CMOS Standard Cell Library using Synopsys Design Compiler. The synthesis result was about 11.9K logic gates and 1078 byte internal SRAM and the maximum operating frequency was 107Mhz. It consumes 879,617 clocks to process one QCIF frame, which means it can process 121.5 QCIF$(176\times144)$ frames per second, therefore it shows that it can be used for real time H.264/AVC encoding of various multimedia applications.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.39 no.4
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• pp.173-179
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• 2002

This paper describes an equalizer using the DFE (Decision Feedback Equalizer) structure, CMA (Constant Modulus Algorithm) and LMS (Least Mean Square) algorithms. The DFE structure has better channel adaptive performance and lower BER than the transversal structure. The proposed equalizer can be used for 16/64 QAM modems. We employ high speed multipliers, square logics and many CSAs (Carry Save Adder) for high speed operations. We have developed floating-point models and fixed-point models using the COSSAP$\^$TM/ CAD tool and developed VHDL filter. The proposed equalizer shows low BER in multipath fading channel. We have performed models. From the simulation results, we employ a 12 tap feedback filter and a 8 tap feedforward logic synthesis using the SYNOPSYS$\^$TM/ CAD tool and the SAMSUNG 0.5$\mu\textrm{m}$ standard cell library (STD80) and verified function and timing simulations. The total number of gates is about 130,000.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.2
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• pp.63-71
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• 2002

This paper suggests a 8-bit RISC microcontroller, which has a 4-stage pipeline architecture. Many low-power design techniques that have been proposed by previous works are adopted into it. The proposed microcontroller consumes only 600㎼ per MIPS for 0.6 ${\mu}{\textrm}{m}$ CMOS process and even lower power of 70㎼ per MIPS for 0.25${\mu}{\textrm}{m}$ process. The RTL level design of this microcontroller is carried out using VHDL. The functional verification is thoroughly done at the gate level using 0.6${\mu}{\textrm}{m}$/0.25${\mu}{\textrm}{m}$ CMOS IDEC standard cell library. This microcontroller contains 7000 NAND gates on a 0.36$\textrm{mm}^2$ die using 0.25${\mu}{\textrm}{m}$ process. Finally the comparison of power consumption with other conventional microcontrollers is provided.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.12
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• pp.234-241
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• 2012

This paper proposes a novel design methodology considering transistor layout variation. The proposed design technique is to improve the transistor's electrical characteristics without performing a circuit simulation to extract transistor layout variation. There are three advantages in the proposed method. Firstly, there is no need to change the normal design flow used in layout designs. Secondly, there is no need to perform simulation in order to extract the transistor layout variation. Thirdly, early warnings in layout design lead to decreasing the number of post layout simulations. Less post layout simulations will decrease the number of iterations in the design cycle and shorten design period. The number of bad transistors in the early design phase were reduced from 17.8% to 2.9% by applying eDRC environment for layout designers to develop Standard Cell Library.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.12
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• pp.27-35
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• 1999

In a typical spread spectrum system, parallel correlator occupies a large fraction of power consumption because of the large number of accumulators in the system. In this paper, a novel accumulator is proposed that can reduce the power consumption in the parallel correlator. The proposed accumulator counts the numbers of 1 of the incoming input data. The counted values are weighted and added together to obtain the final correlation value only at the end of the accumulation. The proposed accumulator has been designed and simulated by CADENCE Verilog-XL and synthesized by SYNOPSYS Design Compiler with $0.6{\mu}m$ standard cell library. Power consumption results have been obtained from EPIC PowerMill simulations. Simulation results are very encouraging. First, the power dissipation is reduced by 22% and the maximum operating frequency is increased by 323%. In addition, the parallel correlator using the proposed accumulators consumed less power than the conventional active parallel correlators by 22%, and less power than the conventional passive correlator by 43%.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.6C
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• pp.594-600
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• 2002

A data manipulation unit capable of bit partitioned shift and various multimedia data type conversions in addition to conventional shift, is presented. Utilizing the similarity between the data type conversion and the shift, the addition of small amount of interconnections to conventional barrel shifter enables data type conversion as well as shift operations with minimal hardware overhead. The presented data manipulation unit is composed of the shifter block for conventional shift and a pack and a unpack block. It has been designed with verilog HDL and the VLSI implementation results using compass 0.6 um standard cell are discussed.