• Journal of KIISE:Information Networking
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• v.37 no.3
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• pp.217-227
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• 2010

To apply active RFID technology in the various kinds of industry, it needs to quickly transmit a large amount of data. ISO/IEC 18000-7 standard uses the 433.92MHz as single channel system and its transmit rate is just 27.8kbps, that is insufficient for a large amount of data transmission. To solve this problem, we designed a new data transmission protocol using 2.4GHz band. The feature of designed protocol is not only making over 255bytes data messages using the Burst Read UDB but also efficiently transmitting it. To implement this protocol, we use Texas Instruments's SmartRF04 develop kit and CC2500 transceiver as RF module. As an evaluation of 63.75kbytes data transmission, we demonstrate that transmission time of Burst Read UDB has improved as 17.95% faster than that of Read UDB in the ISO/IEC 18000-7.

• Journal of IKEEE
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• v.21 no.2
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• pp.146-149
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• 2017

In this paper, we propose a wide-range radiation measurement system using GM Tube and NaI(TI) detector. The proposed system is designed as a small module optimized to control and count the detector signal of NaI(Tl) Detector and GM Tube. The radiation dose is measured in a wide-range 0.1uSv/h to 10mSv/h in conjunction with two detectors, and two detectors operate simultaneously at 10uSv/h to 100uSv/h, where the measurement interval overlaps. The radiation dose was selected using a wide-range radiation measurement algorithm that controls the on/off function of the detector in the appropriate interval for the overlapped radiation measurable interval. In order to evaluate the performance of the proposed system, it has been confirmed that the measurement uncertainty of each section is measured as ${\pm}7.5%$ and it operates normally under ${\pm}15%$ of the international standard.

• The Journal of The Korea Institute of Intelligent Transport Systems
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• v.10 no.2
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• pp.77-83
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• 2011

In this paper, we present the design procedure of the synchronizer and the demodulator of a 13.56MHz RFID PJM tag, which was standardized in ISO 18000-3 mode 3. We optimize the algorithms in order to minimize the number of registers and implement them based on international standard. The designed module is simulated by Modelsim and FPGA. The synchronizer is composed of 3 correlators that is implemented by 1,024(16bit ${\times}$ 64cycle) registers. The demodulator is composed of 2 correlators that is implemented by 128(2bit ${\times}$ 64cycle) registers. The simulation performed with the demodulator integrated with the synchronizer shows that it works at about 87% success rate with the test data of SNR -2dB and 100% with those of SNR 4dB.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.8 no.4
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• pp.59-65
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• 2008

This paper proposed a H.264 deblocking filter for the portable low-power multimedia. In H.264 deblocking filter, total 8 input pixels in filtering operations needs own filtering operation process respectively, and each filtering process has common structures for each filtering operation. By sharing common filter coefficients and registers, we have designed and implemented an smaller gated module, and moreover filtering operations are skipped on some or whole pixels what if we use some specific condition to operate filtering modules that need lots of operations. In the core of filtering modules, we achieve 33.31% and 10.85% gate count reduction compared with those of filtering modules of the conventional deblocking filter papers. The proposed low-power deblocking filter is implemented by using samsung 0.35um standard cell library technology, the maximum operationh frequency is 108MHz, and the maximum throughput is 33.03 frames/s with CCIR601 image format.

• Journal of Power Electronics
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• v.10 no.1
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• pp.9-13
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• 2010

This paper proposes an input-series-output-parallel connected ZVS full bridge converter with interleaved control for photovoltaic power conditioning systems (PV PCS). The input-series connection enables a fully modular power-system architecture, where low voltage and standard power modules can be connected in any combination at the input and/or at the output, to realize any given specifications. Further, the input-series connection enables the use of low-voltage MOSFETs that are optimized for a very low RDSON, thus, resulting in lower conduction losses. The system costs decrease due to the reduced current, and the volumes of the output filters due to the interleaving technique. A topology for a photovoltaic (PV) dc/dc converter that can dramatically reduce the power rating and increase the efficiency of a PV system by analyzing the PV module characteristics is proposed. The control scheme, consisting of an output voltage loop, a current loop and input voltage balancing loops, is proposed to achieve input voltage sharing and output current sharing. The total PV system is implemented for a 10-kW PV power conditioning system (PCS). This system has a dc/dc converter with a 3.6-kW power rating. It is only one-third of the total PV PCS power. A 3.6-kW prototype PV dc/dc converter is introduced to experimentally verify the proposed topology. In addition, experimental results show that the proposed topology exhibits good performance.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.6A
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• pp.555-561
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• 2002

In this paper, a new designed circuit of highly parallel multiplier using standard basis over $GF(2^m)$ is presented. Prior to construct the multiplier circuit, we provide the Vector Code Generate Module(VCGM) that generate each vector codes for multiplication. Using these VCGMs, we can get all vector codes necessary for operation and modular sum up each independent corresponding basis, respectively. Following the equations in this paper, we can design generalized multiplier to m. For the proposed circuit in this parer, we show the example in $GF(2^4)$ using VCGMs. In this paper, we build a multiplier with VCGMs, AND blocks, and EX-OR blocks. Therefore the proposed circuit is easy to generalize for m and advantageous for VLSI. Also, it need no memory element and the latency not less fewer then other circuit. We verify the proposed circuit by functional simulation and show its result. Finally, we compare the circuit composition with other works and show its result with a table.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.3
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• pp.55-61
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• 2000

This paper presents an efficient hardware architecture of frame memory interface in MPEG-2 video encoder. To reduce the size of memory buffers between SDRAM and the frame memory module, the number of clocks needed for each memory access is minimized with dual bank operation and burst length change. By allocating the remaining cycles not used by SDRAM access, to the random access cycle, the internal buffer size, the data bus width, and the size of the control logic can be minimized. The proposed architecture is operated with 54MHz clock and designed with the VT $I^{тм}$ 0.5 ${\mu}{\textrm}{m}$ CMOS TLM standard cell library. It is verified by comparing the test vectors generated by the c-code model with the simulation results of the synthesized circuit. The buffer area of the proposed architecture is reduced to 40 % of the existing architecture.

• Journal of the Korean Society of Manufacturing Process Engineers
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• v.14 no.4
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• pp.151-159
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• 2015

In this study, we developed an automated contact-type thickness measurement machine that continuously and precisely measures the thickness of a PCB module product using multi-LVDT sensors. The system contains a measurement part to automatically measure the thickness in real time according to the set conditions with an alignment supply unit and unloading unit to separate OK and NG products. The sensors were calibrated before assembly in the measuring machine, and precision and accuracy performance tests were also performed to reduce uncertainty errors in the measurement machine. In the calibration test, the precision errors of the LVDT sensor were determined to be $1-3{\mu}m$ as 0.1% at the measuring range. A measurement error of 0.8 mm and 1.0 mm thickness test standards were found to be $1{\mu}m$ and $4{\mu}m$, and the standard deviations of two 1.0 mm products were measured as $14{\mu}m$ and $8{\mu}m$, respectively. In the measurement system analysis, the accuracies of test PCB standards were found to be $2{\mu}m$ and $3{\mu}m$, respectively. From the results of gage repeatability and reproducibility (R & R) crossed, we found that the machine is suitable for the measurement and process control in the mass production line as 7.92% of total gage R & R and in seven distinct categories. The maximum operating speed was limited at 13 pcs/min, showing a value good enough to measure.

• Journal of the Korean Society for Precision Engineering
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• v.15 no.2
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• pp.124-133
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• 1998

This paper describes a research work of developing a computer-aided design of blanking and piercing for irregular-shaped sheet metal products. An approach to the development of compact and practical CAB system is based on the knowledge-based rules. Knowledge for the CAD system is formulated from plasticity theories, experimental results and the empirical knowledge of field experts. The system has been written in AutoLISP on the AutoCAD with a personal computer. Based on knowledge-based rules, the system, STRT-DES, is designed by considering several factors, such as complexities of blank geometry and punch profile, availability of press equipment and standard parts, utilization ratio which minimizes the scrap in a single or a pairwise operation, bridge width, grain orientation and design requirements which maximize the strength of the part when subsequent bending is involved. This system checks a forming feasibility with both internal and external features, a dimension of blanked hole, and a corner and a fillet radius for irregualrly shaped sheet metal products. Therefore this system can carry out a die design for each process which is obtained from results of an automated blank layout drawing with a best utilization ratio for irregular shape of product that was successful in production feasibility check module and those of an automated strip layout drawing and generate part drawings and the assembly drawing of die set in graphic forms.

• Journal of the Korean Society for Precision Engineering
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• v.28 no.2
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• pp.176-184
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• 2011

As modern megalopolises become more complex and huge, convenience and safety of citizens are main components for a welfare state. In order to make safe society, telemetrics technology, which remotely measures the information of target system using electronic devices, is an essential component. In general, telemetrics technology consists of USN (ubiquitous sensor network) based on a wireless network, smart sensor, and SoC (system on chip). In the smart sensor technology, the following two problems should be overcome. Firstly, because it is very difficult for transducer manufacturers to develop smart sensors that support all the existing network protocols, the smart sensor must be independent of the type of networking protocols. Secondly, smart sensors should be modular so that a faulty sensor element can be replaced without replacing healthy communication element. To solve these problems, this paper investigates the feasibility of an IEEE 1451 based ZigBee smart sensor system. More specifically, a smart sensor for large network coverage has been developed using ZigBee for active telemetrics.