• Title/Summary/Keyword: Standard Capacitor

Search Result 102, Processing Time 0.023 seconds

A bio-sensor SoC Platform Using Carbon Nanotube Sensor Arrays (CNT 배열을 이용한 bio-sensor SoC 설계)

  • Chung, In-Young
    • Journal of the Institute of Electronics Engineers of Korea SD
    • /
    • v.45 no.12
    • /
    • pp.8-14
    • /
    • 2008
  • A fully CMOS-integrated carbon nanotube (CNT) sensor array is proposed. After the sensor chip is fabricated in commercial CMOS process, the CNTs network is formed on the top of the fabricated sensor chip through the room-temperature post-CMOS processes. When the resistance of the CNT is changed by the chemical reaction, the read-out circuit in the chip measures the charging time of the $R_{CNT}$-Capacitor. finally the information of measured frequency is converted to a digital code. The CMOS sensor chip was fabricated by standard 0.18um technology and the size of the $8{\times}8$ sensor array is $2mm{\times}2mn$. We have carried out an experiment detecting the biochemical material, glutamate, using this sensor chip. From the experiment the CMOS sensor chip shows the feasibility of sensor for the simultaneous detection of the various target materials.

An Economic Evaluation under Thailand Feed in Tariff of Residential Roof Top Photovoltaic Grid Connected System with Energy Storage for Voltage Stability Improving

  • Treephak, Kasem;Saelao, Jerawan;Patcharaprakiti, Nopporn
    • International Journal of Advanced Culture Technology
    • /
    • v.3 no.1
    • /
    • pp.120-128
    • /
    • 2015
  • In this paper, Residential roof top photovoltaic system with 9.9 kW design is proposed. The system composed of 200 Watts solar array 33 panels connecting in series 10 strings and parallels 3 strings which have maximum voltage and current are 350 V and 23.8 A. The 10 kW sinusoidal grid-connected inverter with window voltage about 270-350 is selected to convert and transfer DC Power to AC Power at PCC (Point of Common Coupling) of power system following to utility standard. However the impact of fluctuation and uncertainty of weather condition of PV may decrease the voltage stability and voltage collapse of power system. In order to solve this problem the energy storage such 120 V 1200 Ah battery bank and 30 kVAR capacitor are designed for voltage stability control. The other expensed for installing the system such battery charger, cable, accessories and maintenance cost are concerned. The economic analysis by using investment from money loan with interest about 7% and use own money which loss income of deposit about 3% are calculated as 671,844 and 547,044 for PV system with energy storage and non energy storage respectively. The solar energy from PV is about 101,616 Bath per year which evaluated by using the value of $5kWh/m^2/day$ from average peak sun hour (PSH) of the Thailand and 6.96 Bath/kWh of Feed in Tariff Incentive. The payback periods of four scenarios are proposed follow as i) PV system with energy storage and use loan money is 15 years ii) PV system with no energy storage and use loan money is 10 years iii) PV system with energy storage and use deposit money is 9 years iv) PV system with energy storage and use deposit money is 7 years. In addition, the other scenarios of economic analysis such no FIT support and other type of economic analysis such NPV and IRR are proposed in this paper.

An Active Voltage Doubling Rectifier with Unbalanced-Biased Comparators for Piezoelectric Energy Harvesters

  • Liu, Lianxi;Mu, Junchao;Yuan, Wenzhi;Tu, Wei;Zhu, Zhangming;Yang, Yintang
    • Journal of Power Electronics
    • /
    • v.16 no.3
    • /
    • pp.1226-1235
    • /
    • 2016
  • For wearable health monitoring systems, a fundamental problem is the limited space for storing energy, which can be translated into a short operational life. In this paper, a highly efficient active voltage doubling rectifier with a wide input range for micro-piezoelectric energy harvesting systems is proposed. To obtain a higher output voltage, the Dickson charge pump topology is chosen in this design. By replacing the passive diodes with unbalanced-biased comparator-controlled active counterparts, the proposed rectifier minimizes the voltage losses along the conduction path and solves the reverse leakage problem caused by conventional comparator-controlled active diodes. To improve the rectifier input voltage sensitivity and decrease the minimum operational input voltage, two low power common-gate comparators are introduced in the proposed design. To keep the comparator from oscillating, a positive feedback loop formed by the capacitor C is added to it. Based on the SMIC 0.18-μm standard CMOS process, the proposed rectifier is simulated and implemented. The area of the whole chip is 0.91×0.97 mm2, while the rectifier core occupies only 13% of this area. The measured results show that the proposed rectifier can operate properly with input amplitudes ranging from 0.2 to 1.0V and with frequencies ranging from 20 to 3000 Hz. The proposed rectifier can achieve a 92.5% power conversion efficiency (PCE) with input amplitudes equal to 0.6 V at 200 Hz. The voltage conversion efficiency (VCE) is around 93% for input amplitudes greater than 0.3 V and load resistances larger than 20kΩ.

Detection Technique of Partial Discharge by a Capacitive Probe in Cast-resin Transformers (몰드변압기에서 용량성 프로브에 의한 부분방전 검출 기술)

  • Jung, Kwang-Seok;Park, Dae-Won;Cha, Hyeon-Kyu;Cha, Sang-Wook;Kil, Gyung-Suk
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
    • /
    • v.24 no.4
    • /
    • pp.319-324
    • /
    • 2011
  • This paper dealt with a partial discharge (PD) detection method for insulation diagnosis in cast-resin transformers. To detect PD pulse, a planar-capacitive probe was designed and fabricated. The probe has no insulation problem and can be installed on cast-resin transformers even in operation since it does not connect with high voltage conductor. The PD measurement system consists of the capacitive probe, a coupling network of 100 [kHz] low-cutoff frequency, and an amplifier with a gain of 40 [dB] and a frequency bandwidth of 500 [Hz]~45 [MHz]. A plane-needle and a plane-plane electrode system were fabricated to simulate insulation defects in a cast-resin transformer. Sensitivity of the PD measurement system, which is evaluated by a standard calibrator was 0.35 [mV/pC] for positive and 0.45 [mV/pC] for negative, respectively. The PD detection by the capacitive probe was less sensitive than that by a coupling capacitor according to IEC 60270, but we could analyze the magnitude and the phase distribution of PD pulse.

Optimal Location of FACTS Devices Using Adaptive Particle Swarm Optimization Hybrid with Simulated Annealing

  • Ajami, Ali;Aghajani, Gh.;Pourmahmood, M.
    • Journal of Electrical Engineering and Technology
    • /
    • v.5 no.2
    • /
    • pp.179-190
    • /
    • 2010
  • This paper describes a new stochastic heuristic algorithm in engineering problem optimization especially in power system applications. An improved particle swarm optimization (PSO) called adaptive particle swarm optimization (APSO), mixed with simulated annealing (SA), is introduced and referred to as APSO-SA. This algorithm uses a novel PSO algorithm (APSO) to increase the convergence rate and incorporate the ability of SA to avoid being trapped in a local optimum. The APSO-SA algorithm efficiency is verified using some benchmark functions. This paper presents the application of APSO-SA to find the optimal location, type and size of flexible AC transmission system devices. Two types of FACTS devices, the thyristor controlled series capacitor (TCSC) and the static VAR compensator (SVC), are considered. The main objectives of the presented method are increasing the voltage stability index and over load factor, decreasing the cost of investment and total real power losses in the power system. In this regard, two cases are considered: single-type devices (same type of FACTS devices) and multi-type devices (combination of TCSC, SVC). Using the proposed method, the locations, type and sizes of FACTS devices are obtained to reach the optimal objective function. The APSO-SA is used to solve the above non.linear programming optimization problem for better accuracy and fast convergence and its results are compared with results of conventional PSO. The presented method expands the search space, improves performance and accelerates to the speed convergence, in comparison with the conventional PSO algorithm. The optimization results are compared with the standard PSO method. This comparison confirms the efficiency and validity of the proposed method. The proposed approach is examined and tested on IEEE 14 bus systems by MATLAB software. Numerical results demonstrate that the APSO-SA is fast and has a much lower computational cost.

Input LC Fiter Design of Diode Rectifiers Considering Filter VA Rating Reduction (필터소자의 용량 저감을 고려한 다이오드 정류기의 입력LC필터 설계)

  • 임영철;정영국
    • Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
    • /
    • v.12 no.1
    • /
    • pp.35-44
    • /
    • 1998
  • In this paper, input LC filter design of diode rectifiers considering filter V A rating reduction has been propoesd. It consisted of an input LC parallel resonent tank whose inductor and capacitor values are se$.$ lected so that the input filter presents an infinite impedance to harmonic input ac current component. The operation of proposed input filter has been analyzed in detail under steady state conditions. Performance evaluation and related design data have been provided on Per Unit basis for the proper implementation of diode rectification system. Finally, Detailed input and output current analysis has shown that the proposed input filter yield high quality input ac current waveforms, in particular, high input power factor values and more reliabilty which reducing the V A rating of passive components as compared to the standard type LC filter.filter.

  • PDF

Design of a 5.2GHz/2.4GHz Dual band CMOS Frequency Synthesizer for WLAN (WLAN을 위한 5.2GHz/2.4GHz 이중대역 주차수 합성기의 설계)

  • Kim, Kwang-Il;Lee, Sang-Cheol;Yoon, Kwang-Sub;Kim, Seok-Jin
    • The Journal of Korean Institute of Communications and Information Sciences
    • /
    • v.32 no.1A
    • /
    • pp.134-141
    • /
    • 2007
  • This paper presents a frequency synthesizer(FS) for 5.2GHz/2.4GHz dual band wireless applications which is designed in a standard $0.18{\mu}m$ CMOS1P6M process. The 2.4GHz frequency is obtained from the 5.2GHz output frequency of Voltage Controlled Oscillator (VCO) by using the Switched Capacitor (SC) and the divider-by-2. Power dissipations of the proposed FS and VCO are 25mW and 3.6mW, respectively. The tuning range of VCO is 700MHz and the locking time is $4{\mu}s$. The simulated phase noise of PLL is -101.36dBc/Hz at 200kHz offset frequency from 5.0GHz with SCA circuit on.

Electric Arc Furnace Voltage Flicker Mitigation by Applying a Predictive Method with Closed Loop Control of the TCR/FC Compensator

  • Kiyoumarsi, Arash;Ataei, Mohhamad;Hooshmand, Rahmat-Allah;Kolagar, Arash Dehestani
    • Journal of Electrical Engineering and Technology
    • /
    • v.5 no.1
    • /
    • pp.116-128
    • /
    • 2010
  • Modeling of the three phase electric arc furnace and its voltage flicker mitigation are the purposes of this paper. For modeling of the electric arc furnace, at first, the arc is modeled by using current-voltage characteristic of a real arc. Then, the arc random characteristic has been taken into account by modulating the ac voltage via a band limited white noise. The electric arc furnace compensation with static VAr compensator, Thyristor Controlled Reactor combined with a Fixed Capacitor bank (TCR/FC), is discussed for closed loop control of the compensator. Instantaneous flicker sensation curves, before and after accomplishing compensation, are measured based on IEC standard. A new method for controlling TCR/FC compensator is proposed. This method is based on applying a predictive approach with closed loop control of the TCR/FC. In this method, by using the previous samples of the load reactive power, the future values of the load reactive power are predicted in order to consider the time delay in the compensator control. Also, in closed loop control, two different approaches are considered. The former is based on voltage regulation at the point of common coupling (PCC) and the later is based on enhancement of power factor at PCC. Finally, in order to show the effectiveness of the proposed methodology, the simulation results are provided.

High Performance Current-Mode DC-DC Boost Converter in BiCMOS Integrated Circuits

  • Lee, Chan-Soo;Kim, Eui-Jin;Gendensuren, Munkhsuld;Kim, Nam-Soo;Na, Kee-Yeol
    • Transactions on Electrical and Electronic Materials
    • /
    • v.12 no.6
    • /
    • pp.262-266
    • /
    • 2011
  • A simulation study of a current-mode direct current (DC)-DC boost converter is presented in this paper. This converter, with a fully-integrated power module, is implemented by using bipolar complementary metal-oxide semiconductor (BiCMOS) technology. The current-sensing circuit has an op-amp to achieve high accuracy. With the sense metal-oxide semiconductor field-effect transistor (MOSFET) in the current sensor, the sensed inductor current with the internal ramp signal can be used for feedback control. In addition, BiCMOS technology is applied to the converter, for accurate current sensing and low power consumption. The DC-DC converter is designed with a standard 0.35 ${\mu}m$ BiCMOS process. The off-chip inductor-capacitor (LC) filter is operated with an inductance of 1 mH and a capacitance of 12.5 nF. Simulation results show the high performance of the current-sensing circuit and the validity of the BiCMOS converter. The output voltage is found to be 4.1 V with a ripple ratio of 1.5% at the duty ratio of 0.3. The sensing current is measured to be within 1 mA and follows to fit the order of the aspect ratio, between sensing and power FET.

Development of PC-based and portable high speed impedance analyzer for biosensor (바이오센서를 위한 PC 기반의 휴대용 고속 임피던스 분석기 개발)

  • Kim, Gi-Ryon;Kim, Gwang-Nyeon;Heo, Seung-Deok;Lee, Seung-Hoon;Choi, Byeong-Cheol;Kim, Cheol-Han;Jeon, Gye-Rok;Jung, Dong-Keun
    • Journal of Sensor Science and Technology
    • /
    • v.14 no.1
    • /
    • pp.33-41
    • /
    • 2005
  • For more convenient electrode-electrolyte interface impedance analysis in biosensor, a stand-alone impedance measurement system is required. In our study, we developed a PC-based portable system to analyze impedance of the electrochemical cell using microprocessor. The devised system consists of signal generator, programmable amplifiers, A/D converter, low pass filter, potentiostat, I/V converter, microprocessor, and PC interface. As a microprocessor, PIC16F877 which has the processing speed of 5 MIPS was used. For data acquisition, the sampling rate at 40 k samples/sec, resolution of 12 bit is used. RS-232 with 115.2 kbps speed is used for the PC communication. The square wave was used as stimuli signal for impedance analysis and voltage-controlled current measurement method of three-electrode-method were adopted. Acquired voltage and current data are calculated to multifrequency impedance signal after Fourier transform. To evaluate the implemented system, we set up the dummy cell as equivalent circuit of which was composed of resistor, parallel circuit of capacitor and resistor connected in parallel and measured the impedance of the dummy cell; the result showed that there exist accuracy within 5 % errors and reproduction within 1 % errors compared to output of Hioki LCR tester and HP impedance analyzer as a standard product. These results imply that it is possible to analyze electrode-electrolyte interface impedance quantitatively in biosensor and to implement the more portable high speed impedance analysis system compared to existing systems.