• 품질경영학회지
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• 제42권3호
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• pp.279-290
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• 2014

Purpose: The purpose of this study is to propose adoption of QFD and Stage-gate in order to analyze the quality of korea defense system. Methods: Drawing change data of initial production phase in korea defense system were anlayzed and a practical method was proposed. Results: The results of this study are as follows; Off line Quality Control should be introduced in development phase. Specially, in case of defense system, the best method is QFD(Quality Function Deployment) and Stage-gate process. At first, QFD 1 step defines product planning from VOC(Voice Of Customer), QFD 2 step specifies part planning from product planning, QFD 3 step defines process planning from part planning, QFD 4 step defines production planning from previous process planning. Secondly, Stage-gate process is adopted. This study is proposed 5 stage-gate in case of korea defense development. Gate 1 is located after SFR(System Function Review), Gate 2 is located after PDR(Preliminary Design Review), Gate 3 is located after CDR(Critical Design Review), Gate 4 is located after TRR(Test Readiness Review) and Gate 5 is located before specification documentation submission. Conclusion: Off line QC(Quality Control) in development phase is necessary prior to on line QC(Quality Control) in p roduction phase. For the purpose of off line quality control, QFD(Quality Function Deployment) and Stage-gate process can be adopted.

• 한국산학기술학회논문지
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• 제21권11호
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• pp.226-232
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• 2020

Stage-Gate 프로세스는 신제품을 아이디어에서 출시로 옮기기 위한 개념 및 운영 모델로, 다양한 신제품 개발 및 연구개발사업에 적용되고 있다. Stage-Gate는 신제품을 시장에 출시하는 것을 목표로 하는 시장 지향적 모델이므로, 대구광역시와 시흥시를 대상으로 실증사업을 진행 중인 스마트시티 혁신성장동력 프로젝트의 운영·관리에 적절히 도입 및 응용 가능하다. 또한 스마트시티는 다양한 혁신 기술 간 융·복합적 특성을 갖는데, Stage-Gate 도입 시, 이를 세분화하여 연구 기관별 성과물 중심의 성과 관리가 가능해진다. 따라서 스마트시티 혁신성장동력 프로젝트(NSSCP: National Strategic Smart City Program)는 국가연구개발사업 최초로 투자 효율성 제고와 연구 성과의 품질 향상, 성공적인 실증 및 사업화를 위하여 Stage-Gate를 적용하였다. 본 논문은 State-Gate 도입 1~2차년도 운영 결과를 검토하고 전문 기관, 연구 기관, 관문심사위원의 의견을 분석하여 향후 차년도 평가체계 운영과 타 연구과제에 적용을 위한 보완 및 개선사항을 제시하였다. Stage-Gate 방법론에 과도하게 몰입되어 경직된 운영에 따른 비효율을 경계하고 해당 사업의 실정에 최적화하여 운영한다면, 스마트시티의 융복합·다학제적 특성에 맞게 성과물 유형에 따른 유연한 평가가 가능할 것으로 기대된다.

• 산업경영시스템학회지
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• 제43권2호
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• pp.65-71
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• 2020

Worldwide plant market keeps maintaining steady growth rate and along with this trend, domestic plant market and its contractors also maintain such growing tendency. However, in spite of its external growth, win-win growth of domestic material industry that occupies the biggest share in plant industry cost portion is extremely marginal in reality. Domestic plant material suppliers are required to increase awareness of domestic material brand by securing quality and reliability of international standard through improvement of design quality superior to that of overseas material suppliers. Improvement of design quality of plant material becomes an essential element, not an option, for survival of domestic plant industry and its suppliers. Under this background, in this study, priority and importance by each evaluation index was analyzed by materializing plant design stage through survey of experts and defining evaluation index by each design stage and based on this analysis result, evaluation index of stage-gate based decision-making process that may improve design quality of plant material was suggested. It is considered that by utilizing evaluation index of stage-gate based decision-making process being suggested in this study, effective and efficient decision-making of project decision-makers would be enabled and it would be contributory to improve design quality of plant material.

• 대한전자공학회논문지
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• 제25권5호
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• pp.572-579
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• 1988

In this paper, a system of automatic placement and routing for gate array layout design is proposed. In the placement stage, the circuit is partitioned and using the concept of min-cut slicing, and each partitioned module is placed, so that the routing density over the entire chip be uniformized and the total wiring length be minimized. In the global routing stage, the concept of the probabilistic routing density is introduced to unify the wiring congestions in each channel. In the detailed routing stage, the multi-terminal nets are partitioned into the two-terminal nets. The ordered channel graph is proposed which implies the vertical and the horizontal constranint graphs simultaneously. And using the ordered channel graph, the proposed routing algorithm assigns the signal nets to the tracks. Also the proposed placement and routing algorithms are implimented on IBM/PC-AT to construct PC-level gate array layout system.

• 전자공학회논문지
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• 제51권1호
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• pp.52-56
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• 2014

본 논문은 고효율 전력증폭기는 무선전력전송을 위한 게이트와 드레인 바이어스 조절 회로를 사용하여 설계하였다. 이 조절 회로는 PAE (Power Added Efficiency)를 개선하기 위해 사용되었다. 게이트와 드레인 바이어스 조절 회로는 directional coupler, power detector, and operational amplifier로 구성되어있다. 구동증폭기를 사용하여 고이득 2단 증폭기는 전력증폭기의 낮은 입력단에 사용되었다. 게이트와 드레인 바이어스 조절회로를 사용하여 제안된 전력증폭기는 낮은 전력에서 높은 효율성을 가질 수 있다. PAE는 80.5%까지 향상되었고 출력전력은 40.17dBm이다.

• 한국통신학회논문지
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• 제14권3호
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• pp.189-196
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• 1989

본 논문에서는 BICMOS 게이트 어레이 시스템 구성시 내부의 논리회로 부분은 CMOS 소자로 입출력부는 바이폴라 소자를 이용할 수 있는 공정과 소자 개발을 하고자 하였다. BICMOS게이트 어레이 공정은 폴리게이트 p-well CMOS 공정을 기본으로 하였고, 소자설계의 기본개념은 공정흐름을 복잡하지 않게 하면서 바이폴라, CMOS 소자 각각의 특성을 좋게 하는데 두었다. 시험결과로서, npn1 트랜지스터의 hFE 특성은 120(Ic=1mA) 정도이고, CMOS 소자에서는 n-채널과 p-채널이 각각 1.25um, 1.35um 까지는 short channel effect 현상이 나타나지 않았고, 41stage ring oscillator의 게이트당 delay 시간은 0.8ns이었다.

• 소성∙가공
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• 제12권2호
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• pp.134-140
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• 2003

Polymers such as polypropylene or polyethylene offer a unique feature of producing an integral hinge, which can flex over a million times without causing a failure. With such advantage manufacturing, time and cost required at the assembly stage can be eliminated by injecting the whole part as one piece. However, due to increased fluidity resistance at hinges during molding, several defects such as short shot or premature hinge failure can occur with the improper selection of gate locations. Therefore, it is necessary to optimize flow balancer in injection molding of part with hinges before actually producing molds. In this paper, resin flow patterns depending on several gate positions were investigated by numerical analyses of a simple strip part with a hinge. As a result, we found that the properly determined gate location leads to better resin flow and shorter hesitation time. Finally, injection molding tryouts using a mold that was designed one of the proposed gate systems were conducted using polypropylene that contained 20% talc. The experiment showed that hinges without defects could be produced by using the designed gate location.

• 대한토목학회논문집
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• 제28권3B호
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• pp.297-306
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• 2008

영산호의 배수갑문 확장, 영암호의 배수갑문, 연락수로의 확폭이 영산강 하류부 홍수위 조절에 미치는 영향을 분석하기 위하여, 영산호와 영암호를 하나의 연계시스템으로 구성하여 부정류 해석을 수행하였다. 영산호 배수갑문의 폭, 영암호 배수갑문의 폭, 연락수로의 폭이 현상태인 조건에서, 영산호-영암호 연계운영의 효과는 미미한 것으로 분석되었다. 영산호의 내수위를 낮추기 위해서는 연락수로의 폭과 영암호 배수갑문의 폭을 확장하는 것이 효과적이며, 영산호 배수갑문의 폭을 확장하는 것은 상대적으로 그 영향이 작은 것으로 분석되었다. 연락수로의 폭을 확장하는 것은 영암호의 내수위 상승을 유발하는데, 상승한 영암호의 내수위를 낮추기 위해서는 영암호 배수갑문과 영산호 배수갑문을 함께 확장하는 것이 필요하다. 연락수로의 폭을 확장함으로써 호소간 분기유량을 증대시키면, 연락수로 제수문의 개폐기준 조정을 통해 영산호의 내수위를 효과적으로 조절할 수 있는 것으로 분석되었다.

• ETRI Journal
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• 제31권3호
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• pp.247-253
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• 2009

We propose a Ku-band driver and high-power amplifier monolithic microwave integrated circuits (MMICs) employing a compensating gate bias circuit using a commercial 0.5 ${\mu}m$ GaAs pHEMT technology. The integrated gate bias circuit provides compensation for the threshold voltage and temperature variations as well as independence of the supply voltage variations. A fabricated two-stage Ku-band driver amplifier MMIC exhibits a typical output power of 30.5 dBm and power-added efficiency (PAE) of 37% over a 13.5 GHz to 15.0 GHz frequency band, while a fabricated three-stage Ku-band high-power amplifier MMIC exhibits a maximum saturated output power of 39.25 dBm (8.4 W) and PAE of 22.7% at 14.5 GHz.

• Journal of Information Display
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• 제12권1호
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• pp.61-67
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• 2011

A single-clock-driven shift register and a two-stage buffer are proposed, using p-type, low-temperature polycrystalline silicon thin-film transistors. To eliminate the clock skew problems and to reduce the burden of the interface, only one clock signal was adopted to the shift register circuit, without additional reference voltages. A two-stage, p-type buffer was proposed to drive the gate line load and shows a full-swing output without threshold voltage loss. The shift register and buffer were designed for the 3.31" WVGA ($800{\times}480$) LCD panel, and the fabricated circuits were verified via simulations and measurements.