• Journal of the Korea Institute of Information and Communication Engineering
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• v.25 no.6
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• pp.813-818
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• 2021

This paper proposes an optimized hardware implementation method for existing CIE1931 color gamut control algorithm. Among the post-processing methods of dehazing algorithms, existing algorithm with relatively low computations have the disadvantage of consuming many hardware resources by calculating large bits using Split multiplier in the computation process. The proposed algorithm achieves computational reduction and hardware miniaturization by reducing the predefined two matrix multiplication operations of the existing algorithm to one. And by optimizing the Split multiplier computation, it is implemented more efficient hardware to mount. The hardware was designed in the Verilog HDL language, and the results of logical synthesis using the Xilinx Vivado program were compared to verify real-time processing performance in 4K environments. Furthermore, this paper verifies the performance of the proposed hardware with mounting results on two FPGAs.

• Journal of the Institute of Convergence Signal Processing
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• v.10 no.4
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• pp.267-273
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• 2009

In this paper, we proposed a variable average operation for a WDR(Wide Dynamic Range). The previously proposed average operation [5] improves hardware efficiency and complexity by replacing divider with multiplier. However, the previously proposed method has some weak-points. For example, there are counting horizontal and vertical length, and then the multiplier selects a Mode set by the user when the lengths exactly correspond with the image's size in the Mode. To compensate some weak-points, we change a Mode selection methods as a using the image's total size. Also, we propose another feature that it can be applied to various image sizes. To get a more accurate average, we add an external compensation value. We design the variable average operation using a Verilog-HDL and confirm that the Serial Multiplier's structure is better efficiency than Split Multiplier's structure.

• Journal of Industrial Technology
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• v.31 no.A
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• pp.27-31
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• 2011

In many industrial experiments, some practical constraints often force factors in an experiment to be much harder to change than others. Such an experiment involves randomization restrictions and it can be thought of as split-plot experiment. This paper investigates the path of steepest ascent/descent within a split-plot structure. A method is proposed for calculating the coordinates along the path.

• Journal of the Korea Society of Computer and Information
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• v.25 no.1
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• pp.37-43
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• 2020

In this paper, we propose an efficient AB² multiplication algorithm using SPB(shifted polynomial basis) over finite fields. Using the feature of the SPB, we split the equation for AB² multiplication into two parts. The two partitioned equations are executable at the same time, and we derive an algorithm that processes them in parallel. Then we propose an efficient semi-systolic AB² multiplier based on the proposed algorithm. The proposed multiplier has less area-time (AT) complexity than related multipliers. In detail, the proposed AB² multiplier saves about 94%, 87%, 86% and 83% of the AT complexity of the multipliers of Wei, Wang-Guo, Kim-Lee, Choi-Lee, respectively. Therefore, the proposed multiplier is suitable for VLSI implementation and can be easily adopted as the basic building block for various applications.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.15 no.7
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• pp.2610-2630
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• 2021

The aim of this paper is to propose the alternative algorithm to finish the process in public key cryptography. In general, the proposed method can be selected to finish both of modular exponentiation and point multiplication. Although this method is not the best method in all cases, it may be the most efficient method when the condition responds well to this approach. Assuming that the binary system of the exponent or the multiplier is considered and it is divided into groups, the binary system is in excellent condition when the number of groups is small. Each group is generated from a number of 0 that is adjacent to each other. The main idea behind the proposed method is to convert the exponent or the multiplier as the subtraction between two integers. For these integers, it is impossible that the bit which is equal to 1 will be assigned in the same position. The experiment is split into two sections. The first section is an experiment to examine the modular exponentiation. The results demonstrate that the cost of completing the modular multiplication is decreased if the number of groups is very small. In tables 7 - 9, four modular multiplications are required when there is one group, although number of bits which are equal to 0 in each table is different. The second component is the experiment to examine the point multiplication process in Elliptic Curves Cryptography. The findings demonstrate that if the number of groups is small, the costs to compute point additions are low. In tables 10 - 12, assigning one group is appeared, number of point addition is one when the multiplier of a point is an even number. However, three-point additions are required when the multiplier is an odd number. As a result, the proposed method is an alternative way that should be used when the number of groups is minimal in order to save the costs.

• Journal of IKEEE
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• v.26 no.3
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• pp.401-407
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• 2022

Recently, image processing technology for autonomous driving by recognizing objects and lanes through camera images to realize autonomous vehicles is being studied. Haze reduces the visibility of images captured by the camera and causes malfunctions of autonomous vehicles. To solve this, it is necessary to apply the haze removal function that can be processed in real time to the camera. Therefore, in this paper, the fog removal method of Sim with excellent performance is implemented with hardware capable of real-time processing. The proposed hardware was designed using Verilog HDL, and FPGA was implemented by setting Xilinx's xc7z045-2ffg900 as the target device. As a result of logic synthesis using Xilinx Vivado program, it has a maximum operating frequency of 276.932MHz and a maximum processing speed of 31.279fps in a 4K (4096×2160) high-resolution environment, thus satisfying the real-time processing standard.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.25 no.11
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• pp.1627-1634
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• 2021

This paper introduces a low-power compact ADC circuit for analog Convolutional filter for low-power neural network accelerator SOC. While convolutional neural network accelerators can speed up the learning and inference process, they have drawback of consuming excessive power and occupying large chip area due to large number of multiply-and-accumulate operators when implemented in complex digital circuits. To overcome these drawbacks, we implemented an analog convolutional filter that consists of an analog multiply-and-accumulate arithmetic circuit along with an ADC. This paper is focused on the design optimization of a low-power 8bit SAR ADC for the analog convolutional filter accelerator We demonstrate how to minimize the capacitor-array DAC, an important component of SAR ADC, which is three times smaller than the conventional circuit. The proposed ADC has been fabricated in CMOS 65nm process. It achieves an overall size of 1355.7㎛², power consumption of 2.6㎼ at a frequency of 100MHz, SNDR of 44.19 dB, and ENOB of 7.04bit.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.26 no.5
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• pp.939-951
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• 2002

We propose a new multiscale Galerkin method based on interpolation wavelets for two-dimensional Poisson's and plane elasticity problems. The major contributions of the present work are: 1) full multiresolution numerical analysis is carried out, 2) general boundaries are handled by a fictitious domain method without using a penalty term or the Lagrange multiplier, 3) no special integration rule is necessary unlike in the (bi-)orthogonal wavelet-based methods, and 4) an efficient adaptive scheme is easy to incorporate. Several benchmark-type problems are considered to show the effectiveness and the potentials of the present approach. is 1-2m/s and impact deformation of the electrode depends on the strain rate at that velocity, the dynamic behavior of the sinter-forged Cu-Cr is a key to investigate the impact characteristics of the electrodes. The dynamic response of the material at the high strain rate is obtained from the split Hopkinson pressure bar test using disc-type specimens. Experimental results from both quasi-static and dynamic compressive tests are Interpolated to construct the Johnson-Cook model as the constitutive relation that should be applied to simulation of the dynamic behavior of the electrodes. The impact characteristics of a vacuum interrupter are investigated with computer simulations by changing the value of five parameters such as the initial velocity of a movable electrode, the added mass of a movable electrode, the wipe spring constant, initial offset of a wipe spring and the virtual fixed spring constant.