• Title/Summary/Keyword: Spin processor

Search Result 8, Processing Time 0.026 seconds

Implementation of Low Noise p-HEMT Using Spin processor (Spin processor에 의한 저잡음 p-HEMT 제작)

  • Kim, Song-Gang
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
    • /
    • 2001.05c
    • /
    • pp.148-152
    • /
    • 2001
  • One set of MMIC library has been developed using gate recess etching by spin processor. It is superior than that of dipping Method in the uniformity and the reproducibility of gate recess. A DC characteristics of p-HEMT have a uniform characteristics in the whole wafer than that of dipping method. The low noise p-HEMT with the $0.6{\mu}m$ and $200{\mu}m$ of gate length and gate width, respectivily, has a uniform characteristics of Idss 130~145 mA, conductances 190~220mS/nm, and threshold voltage -0.7~-1.1V in the drain voltage of 2V.

  • PDF

The design of a fuzzy logic controller for the pointing loop of the spin-stabilized platform (자전 안정화 플랫트폼 위치제어용 퍼지 논리 제어기 설계)

  • 유인억;이상정
    • 제어로봇시스템학회:학술대회논문집
    • /
    • 1992.10a
    • /
    • pp.112-116
    • /
    • 1992
  • In this paper, a fuzzy logic controller(FLC) is designed for the pointing loop of the spin-stabilized platform. For the fuzzy inference, a fuzzy accelerator board using the Togai InfraLogic software and digital fuzzy processor(DFP110FC) is designed, and a validation of an algorithm for fuzzy logic control is also presented. The pointing loop of the spin-stabilized platform using FLC has better performance of step responses than a proportional controller in case of same loop hain through the software simulation and the experiment of implemented hardware.

  • PDF

Implementation and Performance Analysis of Efficient Packet Processing Method For DPI (Deep Packet Inspection) System using Dual-Processors (듀얼 프로세서 기반 DPI (Deep Packet Inspection) 엔진을 위한 효율적 패킷 프로세싱 방안 구현 및 성능 분석)

  • Yang, Joon-Ho;Han, Seung-Jae
    • The KIPS Transactions:PartC
    • /
    • v.16C no.4
    • /
    • pp.417-422
    • /
    • 2009
  • Implementation of DPI(Deep Packet Inspection) system on a general purpose multiprocessor platform is an attractive option from the implementation cost point of view, since it does not require high-cost customized hardware. Load balancing has been considered as a primary means to achieve high performance in multi processor systems. We claim, however, that in case of DPI system design simply balancing the load of each processor does not necessarily yield the highest system performance. Instead, we propose a method in which tasks are allocated to processors based on their functions. We implemented the proposed method in dual processor Linux system and compare its performance with the existing load balancing methods. Under the proposed method, one processor is dedicated to deal with interrupt handling and generic packet processing, while another processor is dedicated to DPI processing. According to experimental results, the proposed scheme outperforms the existing schemes by 60%, mainly because of the reduction of cache miss and spin lock occurrences.

An Efficient Processor Synchronization Scheme on Shared Memory Multiprocessor (공유메모리 다중처리기에서 효율적인 프로세서 동기화 기법)

  • 윤석한;원철호;김덕진
    • Journal of the Korean Institute of Telematics and Electronics B
    • /
    • v.32B no.5
    • /
    • pp.683-692
    • /
    • 1995
  • Many kinds of large scale multiprocessing and parallel-processing systems have recently been developed. The contention on the shared data caused by multiple processors may degrade system performance. So, processor synchronization has become one of the important issues in these systems. To solve the synchornization issues, a lot of software and hardware schemes based on spin lock have been proposed. Although software schemes are easy to implement, hardware schemes are preferred in many systems to gain optimized performance. This paper proposes an efficient processor synchronization scheme, called QCX,and describes its design considerations, hardware, algorithm, protocol. Also, in this paper, the performance of QCX has been evaluated with QOLB[5] and LBP[7] using a simulation. The simulation, with varying the number of processor and the contention on shared variables, measured the average execution times of a workload. The simulation results show that the performances of QCX is best when practicability is considered. QCX is more efficient than QOLB and LBP in two aspects. First, the hardware of QCX is more simple and cost-effective because the cache structure need not be changed. Secondly, QCX is more general because it uses a generic atomic instruction.

  • PDF

A Fuzzy Logic Controller Design for the Pointing Loop of the Spin-Stabilized Platform (자전 안정화 플랫트폼 위치제어용 퍼지 논리제어기 설계)

  • 유인억;김병연;이상정
    • Journal of the Korean Institute of Telematics and Electronics B
    • /
    • v.30B no.4
    • /
    • pp.56-66
    • /
    • 1993
  • In this paper, a fuzzy logic controll(FLC) is designed for the pointing loop of the spinstabilized platform. For the fuzzy inference, a fuzzy accelerator board using the Togai InfraLogic software and digital fuzzy processor(DFP110FC) is designed, and a validation of an algorithm for fuzzy logic control is also presented. Through the simulation and the experiment, it can be seen that the designed FLC shows better performance than a conventional controller using the same loop gain.

  • PDF

Energy Consumption Evaluation for Two-Level Cache with Non-Volatile Memory Targeting Mobile Processors

  • Matsuno, Shota;Togawa, Masashi;Yanagisawa, Masao;Kimura, Shinji;Sugibayashi, Tadahiko;Togawa, Nozomu
    • IEIE Transactions on Smart Processing and Computing
    • /
    • v.2 no.4
    • /
    • pp.226-239
    • /
    • 2013
  • A number of systems have several on-chip memories with cache memory being one of them. Conventional cache memory consists of SRAM but the ratio of static energy to the total energy of the memory architecture becomes larger as the leakage power of traditional SRAM increases. Spin-Torque Transfer RAM (STT-RAM), which is a variety of Non-Volatile Memory (NVM), has many advantages over SRAM, such as high density, low leakage power, and non-volatility, but it consumes too much writing energy. This study evaluated a wide range of energy consumptions of a two-level cache using NVM partially on a mobile processor. Through a number of experimental evaluations, it was confirmed that the use of NVM partially in the two-level cache effectively reduces energy consumption significantly.

  • PDF

Real-time Interactive Control of Magnetic Resonance Imaging System Using High-speed Digital Signal Processors (고속 DSP를 이용한 실시간 자기공명영상시스템 제어)

  • 안창범;김휴정;이흥규
    • Journal of the Institute of Electronics Engineers of Korea SC
    • /
    • v.40 no.5
    • /
    • pp.341-349
    • /
    • 2003
  • A real time interactive controller (spectrometer) for magnetic resonance imaging (MRI) system has been developed using high speed digital signal processors (DSP). The controller generates radio frequency (rf) waveforms and audio frequency gradient waveforms and controls multiple receivers for data acquisition. By employing DSPs having high computational power (e.g., TMS320C670l) real time generation of complicated gradient waveforms and interactive control of selection planes are possible, which are important features in real-time imaging of moving organs, e.g., cardiac imaging. The spectrometer was successfully implemented at a 1.5 Tesla whole body MRI system for clinical application. Performance of the spectrometer is verified by various experiments including high- speed imaging such as fast spin echo (FSE) and echo planar imaging (EPI). These high-speed imaging techniques reduce measurement time, however, usually intensify artifact if there is any systematic phase error or jitter in the synchronization between the transmitter, receiver, and gradients.

Design of MRI Spectrometer Using 1 Giga-FLOPS DSP (1-GFLOPS DSP를 이용한 자기공명영상 스펙트로미터 설계)

  • 김휴정;고광혁;이상철;정민영;장경섭;이동훈;이흥규;안창범
    • Investigative Magnetic Resonance Imaging
    • /
    • v.7 no.1
    • /
    • pp.12-21
    • /
    • 2003
  • Purpose : In order to overcome limitations in the existing conventional spectrometer, a new spectrometer with advanced functionalities is designed and implemented. Materials and Methods : We designed a spectrometer using the TMS320C6701 DSP capable of 1 giga floating point operations per second (GFLOPS). The spectrometer can generate continuously varying complicate gradient waveforms by real-time calculation, and select image plane interactively. The designed spectrometer is composed of two parts: one is DSP-based digital control part, and the other is analog part generating gradient and RF waveforms, and performing demodulation of the received RF signal. Each recover board can measure 4 channel FID signals simultaneously for parallel imaging, and provides fast reconstruction using the high speed DSP. Results : The developed spectrometer was installed on a 1.5 Tesla whole body MRI system, and performance was tested by various methods. The accurate phase control required in digital modulation and demodulation was tested, and multi-channel acquisition was examined with phase-array coil imaging. Superior image quality is obtained by the developed spectrometer compared to existing commercial spectrometer especially in the fast spin echo images. Conclusion : Interactive control of the selection planes and real-time generation of gradient waveforms are important functions required for advanced imaging such as spiral scan cardiac imaging. Multi-channel acquisition is also highly demanding for parallel imaging. In this paper a spectrometer having such functionalities is designed and developed using the TMS320C6701 DSP having 1 GFLOPS computational power. Accurate phase control was achieved by the digital modulation and demodulation techniques. Superior image qualities are obtained by the developed spectrometer for various imaging techniques including FSE, GE, and angiography compared to those obtained by the existing commercial spectrometer.

  • PDF