• Proceedings of the KIEE Conference
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• 1998.07a
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• pp.371-374
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• 1998

The construction of the transportation history database system is to serve the scheduling and seat inventory controling. Recently, lots of countries have been faced with the advance era because of the new railway transportation system, like the high speed railway and/or magnetic levitation vehicle system. This can be reasonably translated as those of operators are willing to provide the more various and high quality schedule to the customer. Those operators these ideas make possible to forecast that scheduling process is going to be complicated more and more. The seat inventory control, so to speak Yield Management System(YMS), goes a long way to improve the total passenger revenue at the railway business. The YMS forecasts the number of the last reservation value(DCP# END) and recommends the optimal values on the seat sales. The history database system contains infra-data(ie, train, seat, sales) that will be the foundation of scheduling and seat inventory control application programs. The development of the application programs are reserved to the next step. The database system is installed on the pc platform (IBM compatible), using the DB2(RDBMS). And at next step, the platform and DBMS will be considered whether they can meet the users' requirement or not.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.6B
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• pp.533-543
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• 2003

Recently, according to the rapid increase of Web users, various kinds of Web applications have been being developed. Hence, Web QoS(Quality of Service) becomes a critical issue in the Web services, such as e-commerce, Web hosting, etc. Nevertheless, most Web servers currently process various requests from Web users on a FIFO basis, which can not provide differentiated QoS. This paper presents two approaches to provide differentiated Web QoS. The first is the kernel-level approach, which is adding a real-time scheduling processor to the operating system kernel to maintain the priority of user requests determined by the scheduling processor of Web server. The second is the load-balancing approach, which uses If-level masquerading and tunneling technology to improve reliability and response speed upon user requests.

• The Transactions of the Korea Information Processing Society
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• v.7 no.11S
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• pp.3684-3693
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• 2000

In this paper, performance of a nonblocking high speed packet switch with switching capacity m which adopts a dynamic priority control function (DPCF) of a threshold- based Bernoulli priority jump (TBPJ) scheme is considered. Each input queue has two separate buffers with different sizes for two classes of traffics, delay-sensitive and loss-sensitive traffics, and adopts a TBPJ scheme that is a general state-dependent Bernoulli scheduling scheme. Under the TBP] scheme, a head packet of the delay-sensitive traffic buffer goes into the loss -sensitive traffic buffer with Hernoulli probability p according to systems states that represent the buffer thresholds and the number of packets waiting for scheduling. Performance analysis shows that TBPJ scheme obtains large performance build-up for the delay-sensitive traffic without performance degradation for the loss-sensitive traffic. In addition to, TBP] scheme shows better performance than that of HOL scheme.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2003.05a
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• pp.390-393
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• 2003

In this paper, we study on an implementation of cell scheduler which arbitrates the ATM exchange efficiently and swiftly. The designed ATM cell scheduler of this paper is based on iSLIP scheduling algorithm. It is aimed at the high-speed implementation. The implemented cell scheduler approximately provides 100% throughput for cell scheduling. We present a basic structure for cell scheduler and describe by using the HDL and perform behavior level and timing simulation. The cell scheduler of this paper is designed to support 8-port switch fabric and can expand in 32-port switch fabric. The cell scheduler for supporting the 8-port switch fabric is designed in 2-stage pipelines for the grant and accept stages respectively.

• Convergence Security Journal
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• v.16 no.7
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• pp.159-165
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• 2016

Through the NFV (Network Function Virtualization), companies such as network service providers and carriers have sought to dramatically reduce CAPEX / OPEX by improving the speed of new service provisioning and flexibility of network construction through the S/W-based devices provided by NFV. One of the most important considerations for establishing an NFV network to provide dynamic services is to determine how to dynamically allocate resources (VNFs), the basic building blocks of network services, in the right place. In this paper, we analyzed the latest research trends on VNF node, link allocation, and scheduling in nodes that are required to provide arbitrary NS in NFV framework. In this paper, we also propose VNF scheduling problems that should be studied further in RA (Resource Allocation).

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.9
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• pp.22-32
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• 1997

This paper proposes an imprecise compuitation model for DCT considering QOS of images and a two dimensional DCT architecture for imprecise computations. In case that many processes are scheduling in a hard real time system, the system resources are shared among them. Thus all processes can not be allocated enough system resources (such as processing power and communication bandwidth). The imprecise computtion model can be used to provide scheduling flexibility and various QOS(quality of service)levels, to enhance fault tolerance, and to ensure service continuity in rela time systems. The DCT(discrete cosine transform) is known as one of popular image data compression techniques and adopted in JPEG and MPEG algorithms since the DCT can remove the spatial redundancy of 2-D image data efficiently. Even though many commercial data compression VLSI chips include the DCST hardware, the DCT computation is still a very time-consuming process and a lot of hardware resources are required for the DCT implementation. In this paper the DCT procedure is re-analyzed to fit to imprecise computation model. The test image is simulated on teh base of this model, and the computation time and the quality of restored image are studied. The row-column algorithm is used ot fit the proposed imprecise computation DCT which supports pipeline operatiions by pixel unit, various QOS levels and low speed stroage devices. The architecture has reduced I/O bandwidth which could make its implementation feasible in VLSI. The architecture is proved using a VHDL simulator in architecture level.

• Journal of KIISE:Computer Systems and Theory
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• v.29 no.11
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• pp.601-610
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• 2002

Intra-task voltage scheduling (IntraVS), which adjusts the supply voltage within an individual task boundary, is an effective technique for developing low-power applications. In this paper, we propose a novel intra-task voltage scheduling algorithm for hard real-time applications based on average-case execution time. Unlike the conventional IntraVS algorithm where voltage scaling decisions are based on the worst-case execution cycles, tile proposed algorithm improves the energy efficiency by controlling the execution speed based on average-case execution cycles while meeting the real-time constraints. The experimental results using an MPEG-4 decoder program show that the proposed algorithm reduces the energy consumption by up to 34% over conventional IntraVS algorithm.

• Journal of the Korea Society of Computer and Information
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• v.19 no.5
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• pp.1-10
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• 2014

The proposed scheme schedules given real-time tasks so that energy consumption of multicore processors would be minimized while meeting tasks' deadline and tolerating a permanent fault based on the primary-backup task model. Whereas the previous methods minimize the overlapped time of a primary task and its backup task, the proposed scheme maximizes the overlapped time so as to decrease the core speed as much as possible. It is analytically verified that the proposed scheme minimizes the energy consumption. Also, the proposed scheme saves up to 77% energy consumption of the previous method through experimental performance evaluation.

• International Journal of Automotive Technology
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• v.7 no.3
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• pp.369-375
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• 2006

This paper describes a simple proportional and integral control algorithm for a swirl motor controller and its application. The control algorithm may be complicated in order to have desired performance, such as low steady state errors, fast response time, and relatively low overshoot. At the same time, it should be compact so that it can be easily implemented on a low cost microcontroller, which has no floating-point calculation capability and low computing speed. These conflicting requirements are fulfilled by the proposed control algorithm which consists of a gain scheduling proportional controller and an anti-windup integral controller. The mechanical friction, which is caused by gears and a return spring, varies very nonlinearly according to the angular position of the system. This nonlinear static friction is overcome by the proportional controller, which has a two-dimensional look up gain table. It has error axis and angular position axis. The integral controller is designed not only to minimize the steady state error but also to avoid the windup effect, which may be caused by the saturation of a motor driver. The proposed control algorithm is verified by use of a commercial product to prove the feasibility of the algorithm.

• ETRI Journal
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• v.30 no.2
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• pp.183-193
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• 2008

In this paper, we propose quality of service mechanisms for flow-based routers which have to handle several million flows at wire speed in high-speed networks. Traffic management mechanisms are proposed for guaranteed traffic and non-guaranteed traffic separately, and then the effective harmonization of the two mechanisms is introduced for real networks in which both traffic types are mixed together. A simple non-work-conserving fair queuing algorithm is proposed for guaranteed traffic, and an adaptive flow-based random early drop algorithm is proposed for non-guaranteed traffic. Based on that basic architecture, we propose a dynamic traffic identification method to dynamically prioritize traffic according to the traffic characteristics of applications. In a high-speed router system, the dynamic traffic identification method could be a good alternative to deep packet inspection, which requires handling of the IP packet header and payload. Through numerical analysis, simulation, and a real system experiment, we demonstrate the performance of the proposed mechanisms.