• Computers and Concrete
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• v.13 no.4
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• pp.457-482
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• 2014

This paper summarizes available literature on the optimization of reinforced concrete (RC) beams. The objective of optimization (e.g. minimum cost or weight), the design variables and the constraints considered by different studies vary widely and therefore, different optimization methods have been employed to provide the optimal design of RC beams, whether as isolated structural components or as part of a structural frame. The review of literature suggests that nonlinear deterministic approaches can be efficiently employed to provide optimal design of RC beams, given the small number of variables. This paper also presents spreadsheet implementation of cost optimization of RC beams in the familiar MS Excel environment to illustrate the efficiency of the exhaustive enumeration method for such small discrete search spaces and to promote its use by engineers and researchers. Furthermore, a sensitivity analysis is performed on the contribution of various design parameters to the variability of the overall cost of RC beams.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.3
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• pp.633-637
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• 2005

In this contribution, we developed and improved an existing GF (Galois field) dividing algorithm by suggesting a novel architecture for a finite field divider, which is frequently required for the error correction applications and the security-related applications such as the Reed-Solomon code, elliptic curve encryption/ decryption, is proposed. We utilized the VHDL language to verify the design methodology, and implemented the architecture on an FPGA chip. We suggested the n-bit lookup table method to obtain the throughput of 2m/n cycles, where m is the order of the division polynomial and n is the number of the most significant lookup-bits. By doing this, we extracted the advantages in achieving both high-throughput and less cost of the gate areaon the chip. A pilot FPGA chip was implemented with the case of m=4, n=2. We successfully utilized the Altera's EP20K30ETC144-1 to exhibit the maximum operating clock frequency of 77 MHz.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2009.10a
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• pp.981-984
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• 2009

In this paper, We design RS(255,239) decoder with modified Euclidean algorithm, which show polynomic coefficient state machine instead of calculating coefficients of modified Euclidean algorithm. This design can reduce complexity and implement High-speed Read Solomon decoder. Additionally, we have synthesized with Xilinx XC4VLX60. From synthesis, it can operate at clock frequency of 77.4MHz, and gate count is 20,710.

• Proceedings of the IEEK Conference
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• 2000.07b
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• pp.914-918
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• 2000

In this paper, a next generation high speed QPSK transmitter is designed based on 1.8${\mu}$m design rule. The designed transmitter supports the MPEG2-TS coded packed data for the DAVIC standard. Transmitter is composed of the convolutional coder, the shortened Reed-Solomon coder, and QPSK modulator. The coded packets are modulated in APSK with an RC filter. Especially, Galois Field multiplier with a standard basis is designed with the pipelined parallel architecture. Also, in the QPSK modulator, the RC filter and mixer are simplified into the ROM table, which can improve the performance of the transmitter. The total number of gates for the implemented baseband transmitter is 26,875.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.12
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• pp.2286-2292
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• 2008

In this paper, we design a RS(23,17) decoder for MB-OFDM(Multiband-Orthogonal Frequency Division Multiplexing) system, in which Modified Euclidean(ME) algorithm is adopted for key equation solver block. The proposed decoder has been optimized for MB-OFDM system so that it has less latency and hardware complexity. Additionally, we have implemented the proposed decoder using Verilog HDL and synthesized with Samsung 65nm library. From synthesis results, it can operate at clock frequency of 250MHz, and gate count is 20,710.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.22 no.4
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• pp.378-385
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• 2021

The purpose of this study is to analyze the effects of a comparative process so that students majoring in urban planning and design can develop the ability to present non-physical alternatives along with the ability to present alternatives to a physical environment to solve urban problems. A total of 30 students majoring in urban planning and urban design were analyzed for their satisfaction with their majors, intention to find a job related to their majors, and academic achievement. This was done after conducting a comparative course of living-lab projects utilizing idle space in a region in connection with a major education course for about a year. For the analysis, the four-group design used by Solomon was used to find the differences between students who participated in the class and those who did not. The analysis showed that the students who participated in the comparative course of the living-lab project were highly satisfied with their major and their intention to find a job related to their major. The results of this study suggest that the process of cultivating the ability to work with local residents and merchants to present physical and non-physical alternatives to solve local problems by utilizing the means of living lab projects has a positive effect on the students' attachment to their majors and their self-esteem.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.37 no.7A
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• pp.503-511
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• 2012

In this paper, the performance analysis of telemetering method using delayed frame time diversity (DFTD) as the outer code and Reed-Solomon (RS) code as the inner code is described. DFTD is used to transmit a real-time frame together with a time-delayed frame which was saved in the memory during a defined period. The RS code as a kind of FEC (forward error correction) is serially concatenated with DFTD. This method was applied to the design of telemetry units that have been used for flight tests in a communication environment with deep fading. The data of the flight test for four cases with no applied code, with DFTD only, with the RS code only, and with both DFTD and the RS code are used to analyze the performance. The simulation for time-delay suggests the possibility that all frame errors can be removed. And the results of 12 flight tests show the performance superiority of this new method to compare with the RS code only.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.8C
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• pp.763-770
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• 2006

In this paper, a variable Reed-Solomon(RS) decoder with erasure decoding functionality is designed based on the modified Euclid's algorithm(MEA). The variability of the decoder is implemented through shortening and puncturing based on the RS(124, 108, 8) code, other than the primitive RS(255, 239, 8) code. This leads to shortening the decoding latency. The decoder performs 4-step pipelined operation, where each step is designed to be clocked by an independent clock. Thus by using a faster clock for the MEA block, the complexity and the decoding latency can be reduced. It can support both continuous- and burst-mode decoding. It has been designed in VHDL and synthesized in an FPGA chip, consuming 3,717 logic cells and 2,048-bit memories. The maximum decoding throughput is 33 MByte/sec.

• Journal of KIISE:Computing Practices and Letters
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• v.6 no.4
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• pp.448-456
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• 2000

As the system complexity increases, it is important to develop high-level verification techniques for fast and efficient design verifications. In this research, fast verification techniques for hardware and software co-design systems have been developed by using logic emulation and algorithm-level simulation. For faster and superior functional verification, we partition the system being designed into hardware and software parts, and implement the divided parts by using interface modules. We also propose several hardware design techniques for efficient hardware emulation. Experimental results, obtained by using a Reed-Solomon decoder system, show that our new verification methodology is more than 12,000 times faster than a commercial simulation tool for the modified Euclid's algorithm block and the overall verification time is reduced by more than 50%.

• Journal of Industrial Technology
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• v.25 no.B
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• pp.171-174
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• 2005

In this paper, we propose a new data encoding algorithm for a two-dimensional bar code system. In general, the one-dimensional bar code is just a key which can access detailed information to the host computer database. But the two-dimensional bar code is a new technology which can obtain high density information without access to the host computer database. We implemented the encoding algorithm for Data Matrix bar code which is the most widely used among the many kinds of two-dimensional bar codes in the field of marking using Digital Signal Processor (TMS320C31). The performance of the proposed algorithm is verified by comparing the imprinted symbols on the steel surfaces with the codes which are decoded by a bar code reader.