• ETRI Journal
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• 제35권6호
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• pp.1152-1155
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• 2013

A cost-effective and simple solder on pad (SoP) process is proposed for a fine-pitch microbump interconnection. A novel solder bump maker (SBM) material is applied to form a 60-${\mu}m$ pitch SoP. SBM, which is composed of ternary Sn3.0Ag0.5Cu (SAC305) solder powder and a polymer resin, is a paste material used to perform a fine-pitch SoP through a screen printing method. By optimizing the volumetric ratio of the resin, deoxidizing agent, and SAC305 solder powder, the oxide layers on the solder powder and Cu pads are successfully removed during the bumping process without additional treatment or equipment. Test vehicles with a daisy chain pattern are fabricated to develop the fine-pitch SoP process and evaluate the fine-pitch interconnection. The fabricated Si chip has 6,724 bumps with a 45-${\mu}m$ diameter and 60-${\mu}m$ pitch. The chip is flip chip bonded with a Si substrate using an underfill material with fluxing features. Using the fluxing underfill material is advantageous since it eliminates the flux cleaning process and capillary flow process of the underfill. The optimized bonding process is validated through an electrical characterization of the daisy chain pattern. This work is the first report on a successful operation of a fine-pitch SoP and microbump interconnection using a screen printing process.

• 마이크로전자및패키징학회지
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• 제12권4호통권37호
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• pp.351-357
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• 2005

솔더/UBM 계면반응에 따른 솔더범프의 기계적 신뢰성을 평가하기 위한 방안으로서 Cu UBM 상에서 리플로우한 Sn-52In 솔더범프의 리플로우 조건에 따른 전단응력과 전단에너지의 변화거동을 비교하였다. 리플로우 조건에 따른 전단에너지의 변화거동이 전단강도에 비해 Sn-52In/Cu 계면반응 및 파괴모드의 변화거동과 훨씬 잘 일치하여 솔더/UBM 계면반응에 따른 기계적 신뢰성을 분석하는데 전단에너지가 전단강도보다 훨씬 효과적인 평가 방안임을 알 수 있었다.

• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2003년도 기술심포지움 논문집
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• pp.169-173
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• 2003

We demonstrated the applicability of dry film photoresist (DFR) in photolithography process for fine pitch solder bumping on the polytetrafluoroethylene (PTFE/Teflon) printed circuit board (PCB). The copper lines were formed with $100\;{\mu}m$ width and $18\;{\mu}m$ thickness on the PTFE test board, and varying the gaps between two copper lines in a range of $100-200\;{\mu}m$. The DFRs of $15\;{\mu}m$ thickness were laminated by hot roll laminator, by varying laminating temperature from $100^{\circ}C\;to\;150^{\circ}C$ and laminating speed. We found the optimum process of DFR lamination on PTFE PCB and accomplished the formation of indium solder bumps. The optimum lamination condition was temperature of $150^{\circ}C$ and speed of about 0.63 cm/s. And the smallest size of indium solder bump was diameter of $50\;{\mu}m$ with pitch of $100\;{\mu}m$.

• 대한기계학회:학술대회논문집
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• 대한기계학회 2000년도 춘계학술대회논문집A
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• pp.873-878
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• 2000

Semiconductor packaging technology is changed rapidly according to the trends of the micro miniaturization of multimedia and information equipment. For I/O limitation and fine pitch limitation, DIP and SOP/QFP are replaced by BGA/CSP. This is one of the surface mount technology(SMT). Solder ball is bumped n the die pad and connected onto mounting board. In ball bump formation, vacuum suction type ball alignment process is widely used, However this type has some problems such as ionization, static electricity and difficulty of fifo(first-input first-out) of solder balls. Seesaw type is reducing these problems and has a structural simplicity and economic efficiency. Ball cartridge velocity and ball aligned plate angle are Important variables to improve the ball alignment Process. In this paper, seesaw-type CSP solder ball loader is developed and the optimal velocity and plate angle are proposed.

• 한국공작기계학회논문집
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• 제16권6호
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• pp.181-186
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• 2007

UBM (Under Bump Metallurgy) of flip chip assemblies consists of several layers such as the solder wetting, the diffusion barrier, and the adhesion layers. In addition, IMC layers are formed between the solder wetting layers (e.g. Cu, Ni) and the solder. The primary failure mechanism of the solder joints in flip chips is widely known as the fatigue failure caused by thermal fatigues or electromigration damages. Sometimes, the premature brittle failure occurs in the IMC layers. However, these phenomena have thus far been viewed from only experimental investigations. In this sense, this paper presents a method for solid modeling of IMC layers in flip chip assemblies, thus providing a pre-processing tool for finite element analysis to simulate the IMC failure mechanism. The proposed modeling method is CSG-based and can also be applied to the modeling of UBM structure in flip chip assemblies. This is done by performing Boolean operations according to the actual sequences of fabrication processes

• 마이크로전자및패키징학회지
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• 제18권3호
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• pp.45-52
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• 2011

Flip Chip Ball Grid Array (FCBGA) 패키지의 솔더조인트 신뢰성을 평가하기 위한 방법으로는 다이 충격법, 다이 전단법, 3점 굽힘법, 열충격법 등이 활용된다. 본 연구에서는 솔더 접합부의 주요 고장메카니즘인 취성파괴를 확인하기 위한 방법으로 리플로우 상태, $85^{\circ}C$/85%RH 처리, $150^{\circ}C$/10hr 에이징의 처리한 후, 4가지 평가법으로 평가를 진행하여 파단모드를 분석하였다. 본 연구결과에서는 다이 충격법과 다이 전단법의 Good joint rate (GJR, %)는 리플로우 상태와 $85^{\circ}C$/85%RH처리에서 각각 89~91%와 100% 였으며, $150^{\circ}C$/10hr 에이징에서는 66%와 90%를 나타내었다. 3점 굽힘법과 열충격법의 GJR(%)는 3종류 샘플에서 모두 100%를 나타내어 변별력이 없었다. C4 솔더접합부의 신뢰성 평가법에 따른 GJR(%)의 변별력을 확인할 수 있는 방법은 die shock 과 die shear test였다.

• 한국재료학회지
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• 제24권3호
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• pp.166-173
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• 2014

The effects of printed circuit board electroless nickel immersion gold (ENIG) and organic solderability preservative (OSP) surface finishes on the electromigration reliability and shear strength of Sn-3.5Ag Pb-free solder bump were systematically investigated. In-situ annealing tests were performed in a scanning electron microscope chamber at 130, 150, and $170^{\circ}C$ in order to investigate the growth kinetics of intermetallic compound (IMC). Electromigration lifetime and failure modes were investigated at $150^{\circ}C$ and $1.5{\times}10^5A/cm^2$, while ball shear tests and failure mode analysis were conducted under the high-speed conditions from 10 mm/s to 3000 mm/s. The activation energy of ENIG and OSP surface finishes during annealing were evaluated as 0.84 eV and 0.94 eV, respectively. The solder bumps with ENIG surface finish showed longer electromigration lifetime than OSP surface finish. Shear strengths between ENIG and OSP were similar, and the shear energies decreased with increasing shear speed. Failure analysis showed that electrical and mechanical reliabilities were very closely related to the interfacial IMC stabilities.

• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2003년도 기술심포지움 논문집
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• pp.103-105
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• 2003

COG (Chip on Glass) technology using solder bump reflow has been investigated to attach IC chip directly on glass substrate of LCD panel. As It chip and LCD panel have to be heated to reflow temperature of the so]der bumps for COG bonding, it is necessary to use low-temperature solders to prevent the damage of liquid crystals of LCD panel. In this study, using the Sn-52In solder bumps of $40{\mu}m$ pitch size, solder joints between Si chip and glass substrate were made at temperature below $150^{\circ}C$. The contact resistance of the solder joint was $8.58m\Omega$, which was much lower than that of the joint made using the conventional ACF bonding technique. The Sn-52In solder joints with underfill showed excellent reliability at a hot humid environment.

• Journal of Welding and Joining
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• 제31권6호
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• pp.77-83
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• 2013

3D packaging technology using TSV (Through Silicon Via)has been studied in the recent years to achieve higher performance, lower power consumption and smaller package size because electrical line is shorter electrical resistivity than any other packaging technology. To stack TSV chips vertically, reliable and robust bonding technology is required because mechanical stress and thermal stress cause fracture during the bonding process. Cu pillar/solder ${\mu}$-bump bonding process is usually to interconnect TSV chips vertically although it has weak shape to mechanical stress and thermal stress. In this study, we suggest Insert-Bump (ISB) bonding process newly to stack TSV chips. Through experiments, we tried to find optimal bonding conditions such as bonding temperature and bonding pressure. After ISB bonding, we observed microstructure of bump joint by SEM and then evaluated properties of bump joint by die shear test.

• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2002년도 추계기술심포지움논문집
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• pp.33-37
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• 2002

본 연구에서는 전해도금법을 이용하여 플립칩용 Ni, Ni-Cu 합금 UBM (Under Bump Metallurgy) 및 Sn-Ag 무연 솔더 범프를 형성하였다. 솔더 범프의 전해도금시 고속도금 방법으로 균일한 범프 높이를 갖도록 하는 도금 조건 및 도금 기판의 역할로서의 UBM의 영향을 조사하였다. Cu/Ni-Cu 합금/Cu UBM을 적용한 경우 음극시편의 전극 접점수를 증가시켰을 때 비교적 균일한 솔더 범프를 형성시킬 수 있었던 반면, Ni UBM의 경우는 접점수를 증가시켜도 다소 불균일한 솔더 범프를 형성하였다. 리플로 시간을 변화하여 범프 전단 강도 및 파단 특성을 조사하였는데 Ni UBM의 경우 Cu/Ni-Cu 합금/Cu UBM에 비해 전단강도가 다소 낮은 값을 가졌고 금속막이 웨이퍼에서 분리되는 파괴 거동이 관찰되었다.