• Journal of the Korea Fashion and Costume Design Association
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• v.10 no.3
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• pp.101-110
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• 2008

We believe distinguishable product development to be competitive against foreign products, and realize the need to expand domestic business worldwide. In order to be competitive, we should produce fashion items that meets global taste, and at the same time contain exclusive Korean culture and emotional beauty. This article examines and creates unique textile design with the touch of Korean art. Desigus have been proceeded under the following three themes: 'Strong Ego,' 'Gorgeous Days' and 'Song Eternal Seeking Love' using Primavision Computer-aided Design ("CAD"). We have put our interestes in Korean traditional paintings called Hangukhwa. Suitable design motives had been selected and modified from the four gracious plants (bamboos, peonies etc.), and paintings of birds and flowers. Primavision, a CAD software, had been used to manipulate those desigus, and to add instant changes in color, scale, and layout. We had modified Korean traditional motives to make modem image, and had arranged layouts which can be suitable for half-drop repeat and square repeat. The use of color is essential in pattern design. Thus, we explored coloring ways for each design to meet the trends, and the final mapping had been conducted in western style of dresses. We have tried to mix Korean image of textile designs with Western clothing style, expressing hybrid in the mapping process. With global movements, we need to develop products with Korean traditional exotic taste to attract foreign consumers. Therefore, we selected symbolic motives from Korean paintings to express deep spiritual significance. We developed textile design and processed mapping on selected western designer's dress, employing current trend colors and making crossover coordination. We realized Korean painting would be an excellent source for exclusive fabric design, and tried to create a modernized design which maintains Korean ethnical identities.

• Journal of KIISE:Software and Applications
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• v.33 no.9
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• pp.741-750
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• 2006

In this paper, we propose a method for reconstructing a 3D object (or a set of objects) from a 2D drawing provided by a designer. The input 2D drawing consists of a set of contours that may partially overlap each other or be self-overlapping. Accordingly, the resulting 3D object(s) may occlude each other or be self-occluding. The proposed method is composed of three major steps: 2D contour analysis, 3D skeleton computation, and 3D object construction. Our main contribution is to compute the 3D skeleton from the self-intersecting 2D counterpart. We formulate the 3D skeleton construction problem as a sequence of optimization problems, to shape the skeleton and place it in the 3D space while satisfying C1-continuity and intersection-free conditions. Our method is mainly for a silhouette-based sketching interface for the design of 3D objects including self-intersecting objects.

• Journal of KIISE:Computing Practices and Letters
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• v.5 no.4
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• pp.489-497
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• 1999

국내의 ATM 기술은 대부분 교환기 시스템 개발에 집중되어 있었고 최근에는ATM 서비스 분야에 대한 개발 요구가 있다. 이러한 가운데 Internet 서비스는 데이타 망의 기본 서비스로 자리잡았으며, ATM망도 기본적으로 Internet 서비스를 지원하여야 한다. IETF의 IPOA (Classical IP and ARP over ATM)는 국내 망 여건 및 구현의 용이성으로 Internet 서비스를 위한 프로토콜중 가장 선호 대상이지만 RFC사양의 허술함, 구현자의 사양에 대한 이해 부족과 초기 외산 장비 제조 업체들의 자체 사양때문에 기존의 IPOA장비들과 상호 운용 시험에서 후발 IPOA 개발자는 시행착오를 겪어야만 한다. 본 논문에서는 기존 외산 IPOA 장비들과 자체 개발한 장비와 상호 운용 시험을 수행하면서 겪은 사례 연구를 정리하였고 이를 기초로 기존의 외산 IPOA와 상호 운용할 수 있는 최종 요구 사항을 제시하였다. 본 논문을 기초로 IPOA 장비를 개발한다면 국내 후발 ATM 장비 업체는 개발의 시간 및 노력을 줄일 수 있고 향후 IP/ATM 국내 기술력 향상에 도움이 될 것이다.Abstract While we have been focusing on development of ATM switching systems, recently the demand on service by use of ATM switching system is increasing rapidly. Among various ATM services, the Internet service should be provided in an ATM network since the Internet service has been the basic data service. Many domestic engineers consider the classical IP and ARP over ATM (IPOA) to be an appropriate method for interworking of IP and ATM because the IP is the network protocol used in most domestic data networks, and the IPOA is simpler and has less overhead than other approaches. However, it is not easy for a developer to implement the IPOA function module interoperable with other existing ones due to the incomplete description of IETF's RFC specifications, misunderstanding of designer and/or developer, and incompatible vendors' specifications. In this paper, we show several case studies undertaken for interoperability tests of IPOA products between our product and other vendor's products, and discuss the implementation requirement of the IPOA software to be interoperable with the existing IPOA equipment.The design and implementation requirements presented in this paper will reduce the effort of IPOA-developing engineers and time required for interoperability test. Also, this contribution will be helpful in IP/ATM interworking areas.

• International Journal of Naval Architecture and Ocean Engineering
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• v.7 no.6
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• pp.1044-1055
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• 2015

DPCap analysis can assist in determining the maximum environmental forces the DP system can counteract for a given heading. DPCap analysis results are highly affected by the thrust forces provided by the thrust system which consists of several kinds of thrusters. The thrust forces and moment are determined by the maximum thrust of the thrusters as well as the thruster configuration. In this paper, a novel local optimization of thruster configuration based on a synthesized positioning capability criterion is proposed. The combination of the discrete locations of the thrusters forms the thruster configuration and is the input, and the synthesized positioning capability is the output. The quantified synthesized positioning capability of the corresponding thruster configuration can be generated as the output. The optimal thruster configuration is the one which makes the vessel has the best positioning capability. A software program was developed based on the present study. A local optimization of thruster configuration for a supply vessel was performed to demonstrate the effectiveness and efficiency of the program. Even though the program cannot find the global optimal thruster configuration, its high efficiency makes it essentially practical in an engineering point. It may be used as a marine research tool and give guidance to the designer of the thrust system.

• Journal of the Korean Society for Railway
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• v.10 no.5
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• pp.596-599
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• 2007

A comparative Life Cycle Assessment (LCA) among three types of Electric Motor Unit (EMU) Interior Panel (IP) was conducted. A functional unit for comparative LCA is a weight of IP for 1 EMU. It is assumed that Manufacturing stage and its upstream processes, Use stage and End of Life (EoL) stage are included in the boundary of product system. For Use stage, the weight of IP causes electricity consumption. It is assumed that aluminum IP is recycled and the other IPs are incinerated at the EoL stage. As a comparison results, aluminum IP has much larger environmental impact (5.162pt) than others (FRP IP; 4.069pt, Phenol IP; 4.053pt) even though recycling consideration is included. The manufacturing stage of aluminum IP has relative big environmental impact (1.824pt) and this point make the most important difference from other IPs (FRP IP; 0.1617pt, Phenol IP; 0.4534pt)). Despite of large weight difference between FRP IP (888.96kg) and phenol IP (316kg), the final environmental impact result has only little difference (0.016pt, 0.39%). With this result, the EMU designer can choose IP with a consideration of the environmental performance of IP.

• Journal of the Korea Society of Computer and Information
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• v.15 no.9
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• pp.1-8
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• 2010

The key challenge in HW/SW co-design is how to choose the appropriate HW/SW partitioning from the vast array of possible options in the mapping set. In this paper we present a unique and efficient approach for addressing this problem known as Customized Heuristic Algorithm for Reducing Mapping Sets(CHARMS). CHARMS uses sensitivity to individual task computational complexity as well the computed weighted values of system performance influencing metrics to streamline the mapping sets and extract the most optimal cases. Using H.263 encoder, we show that CHARMS sieves out 95.17% of the sub-optimal mapping sets, leaving the designer with 4.83% of the best cases to select from for run-time implementation.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2014.05a
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• pp.454-457
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• 2014

Arduino is for design based on open source prototyping platform, artist, designer, hobby activists, etc, i has been designed for all those who are interested in the environment construct. Arduino adventage you can easily create applications hardware, without deep knowledge about the hardware. Configuration of arduino using AVR microcontroller ATmage 168, software to action arduino using arduino program, MATLAB, Processing. Arduino is open source base, you can hardware production directly and using shield additionally, the arduino can be combined. Android is open source. Continue to expand through a combination of hardware, Arduino. It name is shield. Be given to the Arduino Uno board to the main board, the shield extends to the various aspects and help can be equipped with more features. The shield on top of the shield can be combined as a kind of shield and Ethernet shield, motor shield, the shield RFID hardware beyond a simple extension can be configured. In this paper, RFID technology Sealed for automatic recognition of the elderly by the elderly to identify and tag them SM130 13.56Mhz compatible hardware was constructed by combining tags.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.8
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• pp.95-101
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• 2009

Random numbers are used in many sorts of applications. Some applications, like simple software simulation tests, communication protocol verifications, cryptography verification and so forth, need various levels of randomness with various process speeds. In this paper, we propose a fast pseudorandom generator module for embedded systems. The generator module is implemented in hardware which can run in two modes, one of which can generate random numbers with higher randomness but which requires six cycles, the other providing its result within one cycle but with less randomness. An ASIP (Application Specific Instruction set Processor) was designed to implement the proposed pseudorandom generator instruction sets. We designed a processor based on the MIPS architecture,, by using LISA, and have run statistical tests passing the sequence of the Diehard test suite. The HDL models of the processor were generated using CoWare's Processor Designer and synthesized into the Dong-bu 0.18um CMOS cell library using the Synopsys Design Compiler. With the proposed pseudorandom generator module, random number generation performance was 239% faster than software model, but the area increased only 2.0% of the proposed ASIP.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 1993.06a
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• pp.975-976
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• 1993

This talk presents the overview of the author's research and development activities on fuzzy inference hardware. We involved it with two distinct approaches. The first approach is to use application specific integrated circuits (ASIC) technology. The fuzzy inference method is directly implemented in silicon. The second approach, which is in its preliminary stage, is to use more conventional microprocessor architecture. Here, we use a quantitative technique used by designer of reduced instruction set computer (RISC) to modify an architecture of a microprocessor. In the ASIC approach, we implemented the most widely used fuzzy inference mechanism directly on silicon. The mechanism is beaded on a max-min compositional rule of inference, and Mandami's method of fuzzy implication. The two VLSI fuzzy inference chips are designed, fabricated, and fully tested. Both used a full-custom CMOS technology. The second and more claborate chip was designed at the University of North Carolina(U C) in cooperation with MCNC. Both VLSI chips had muliple datapaths for rule digital fuzzy inference chips had multiple datapaths for rule evaluation, and they executed multiple fuzzy if-then rules in parallel. The AT & T chip is the first digital fuzzy inference chip in the world. It ran with a 20 MHz clock cycle and achieved an approximately 80.000 Fuzzy Logical inferences Per Second (FLIPS). It stored and executed 16 fuzzy if-then rules. Since it was designed as a proof of concept prototype chip, it had minimal amount of peripheral logic for system integration. UNC/MCNC chip consists of 688,131 transistors of which 476,160 are used for RAM memory. It ran with a 10 MHz clock cycle. The chip has a 3-staged pipeline and initiates a computation of new inference every 64 cycle. This chip achieved an approximately 160,000 FLIPS. The new architecture have the following important improvements from the AT & T chip: Programmable rule set memory (RAM). On-chip fuzzification operation by a table lookup method. On-chip defuzzification operation by a centroid method. Reconfigurable architecture for processing two rule formats. RAM/datapath redundancy for higher yield It can store and execute 51 if-then rule of the following format: IF A and B and C and D Then Do E, and Then Do F. With this format, the chip takes four inputs and produces two outputs. By software reconfiguration, it can store and execute 102 if-then rules of the following simpler format using the same datapath: IF A and B Then Do E. With this format the chip takes two inputs and produces one outputs. We have built two VME-bus board systems based on this chip for Oak Ridge National Laboratory (ORNL). The board is now installed in a robot at ORNL. Researchers uses this board for experiment in autonomous robot navigation. The Fuzzy Logic system board places the Fuzzy chip into a VMEbus environment. High level C language functions hide the operational details of the board from the applications programme . The programmer treats rule memories and fuzzification function memories as local structures passed as parameters to the C functions. ASIC fuzzy inference hardware is extremely fast, but they are limited in generality. Many aspects of the design are limited or fixed. We have proposed to designing a are limited or fixed. We have proposed to designing a fuzzy information processor as an application specific processor using a quantitative approach. The quantitative approach was developed by RISC designers. In effect, we are interested in evaluating the effectiveness of a specialized RISC processor for fuzzy information processing. As the first step, we measured the possible speed-up of a fuzzy inference program based on if-then rules by an introduction of specialized instructions, i.e., min and max instructions. The minimum and maximum operations are heavily used in fuzzy logic applications as fuzzy intersection and union. We performed measurements using a MIPS R3000 as a base micropro essor. The initial result is encouraging. We can achieve as high as a 2.5 increase in inference speed if the R3000 had min and max instructions. Also, they are useful for speeding up other fuzzy operations such as bounded product and bounded sum. The embedded processor's main task is to control some device or process. It usually runs a single or a embedded processer to create an embedded processor for fuzzy control is very effective. Table I shows the measured speed of the inference by a MIPS R3000 microprocessor, a fictitious MIPS R3000 microprocessor with min and max instructions, and a UNC/MCNC ASIC fuzzy inference chip. The software that used on microprocessors is a simulator of the ASIC chip. The first row is the computation time in seconds of 6000 inferences using 51 rules where each fuzzy set is represented by an array of 64 elements. The second row is the time required to perform a single inference. The last row is the fuzzy logical inferences per second (FLIPS) measured for ach device. There is a large gap in run time between the ASIC and software approaches even if we resort to a specialized fuzzy microprocessor. As for design time and cost, these two approaches represent two extremes. An ASIC approach is extremely expensive. It is, therefore, an important research topic to design a specialized computing architecture for fuzzy applications that falls between these two extremes both in run time and design time/cost. TABLEI INFERENCE TIME BY 51 RULES {{{{Time }}{{MIPS R3000 }}{{ASIC }}{{Regular }}{{With min/mix }}{{6000 inference 1 inference FLIPS }}{{125s 20.8ms 48 }}{{49s 8.2ms 122 }}{{0.0038s 6.4㎲ 156,250 }} }}

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.8 no.6
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• pp.159-163
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• 2008

Recently, typography in Korea has been varied. Among them, after 2005 a new trend caligraphy has appeared and in reality people discussed that this has been occurred as a coincidence. However, as a view of one who is interested in Hangeul typography, born of Hangeul caligraphy is not a coincidence. It is because computerizing of Hangeul has been later than U.S. or Japan. Korea was colonized by Japan and experienced the Korean War and economical independence got late and cultural independence got late as well. Our language, Hangeul was independenced in the beginning of 1990's after computer was introduce and original letter of Hangeul was scanned and basic standard was built. From the end of 80's there were many efforts for independence of Hangeul but there were problems on hardware side than software side. In the beginning of 90's basic fonts such as Myungjo or Gothic of Choi Jung-ho's fonts were set for computer hardware, but later 90's can be called as a time for distributing designed fonts for that new fonts that were planned and applying new ideas on fonts were done. In 2000 the two major font company in Korea Sandoll Communication and Yoon Design Institute made a fonts such as When branding had to be done by designer, typo must be written so adjusting size and moving baseline made old style and caligraphy fonts to be born. These cycling process has been natural motive for nowadays' caligraphy and these two major companies' role has made caligraphy to be popular.