• International Journal of Internet, Broadcasting and Communication
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• v.12 no.1
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• pp.90-94
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• 2020

Artificial intelligence (AI) is software that learns large amounts of data and provides the desired results for certain patterns. In other words, learning a large amount of data is very important, and the role of memory in terms of computing systems is important. Massive data means wider bandwidth, and the design of the memory system that can provide it becomes even more important. Providing wide bandwidth in AI systems is also related to power consumption. AlphaGo, for example, consumes 170 kW of power using 1202 CPUs and 176 GPUs. Since more than 50% of the consumption of memory is usually used by system chips, a lot of investment is being made in memory technology for AI chips. MRAM, PRAM, ReRAM and Hybrid RAM are mainly studied. This study presents various memory technologies that are being studied in artificial intelligence chip design. Especially, MRAM and PRAM are commerciallized for the next generation memory. They have two significant advantages that are ultra low power consumption and nearly zero leakage power. This paper describes a comparative analysis of the four representative new memory technologies.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.6
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• pp.736-744
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• 2016

Network on chip (NoC) is an emerging technology in the field of multi core interconnection architecture. The routers plays an essential components of Network on chip and responsible for packet delivery by selecting shortest path between source and destination. State-of-the-art NoC designs used routing table to find the shortest path and supports four ports for packet transfer, which consume high power consumption and degrades the system performance. In this paper, the multi port multi core router architecture is proposed to reduce the power consumption and increasing the throughput of the system. The shared buffer is employed between the multi ports of the router architecture. The performance of the proposed router is analyzed in terms of power and current consumption with conventional methods. The proposed system uses Modelsim software for simulation purposes and Xilinx Project Navigator for synthesis purposes. The proposed architecture consumes 31 mW on CPLD XC2C64A processor.

• Journal of KIISE:Software and Applications
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• v.36 no.5
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• pp.376-385
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• 2009

Increasing the importance of Green IT brings low-power consumption requirements for embedded software into relief. This paper focus on the power analysis techniques of embedded software along with the trend. We survey the existing research on the power analysis techniques performed during the last decade, and find out some features or characteristics from the analysis approaches of those techniques. Also we summarize those characteristics into a systematic model, and then apply the model to embedded software development process using spider diagram. Our suggestion gives such benefits as improving the understanding of power analysis techniques, guiding the choice of an appropriate technique to their Power analysis, and forecasting the direction of technology changes in embedded software power analysis.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.60 no.4
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• pp.871-876
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• 2011

In this paper, a voltage-controlled frequency tunable current-mode integrator and a 3rd-order current-mode Chebyshev filter in 1.8V-$0.18{\mu}m$ CMOS is realized for software radio applications in system-on-chips. This filter is used for reconstruction purposes between a current-steering DAC and a current-mode mixer. Power consumption of the designed filter can be reduced by using a current-mode small size integrator. And also, cutoff frequency of this filter is variable between 1.2MHz and 10.1MHz, the power consumption is 2.85mW. And the voltage bias compensated circuit is used to control the voltage variation.in the designed filter.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.9A
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• pp.1368-1376
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• 2000

This paper describes the codesign method for IS-95 based CDMA(Code Division Multiple Access). By codesign we mean to design hardware and software simultaneously. Codesign lead to reduction in design time, cost and power consumption. When we partition a system into hardware and software, some modules with longer processing time and larger power consumption are implemented using hardware and the remaining part is implemented using software. In proposed design, we design the synchronous accumulator of CDMA searcher in hardware and the other part in software, The hardware part is designed using VHDL, while software part is designed using GC(Generic C). We simulated and verified the system using COSSAP in SYNOPSYSTM. Experimentation showed the maximum 48.5% speed reduction compared with the design using software only.

• Journal of the Korea Society of Computer and Information
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• v.20 no.7
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• pp.57-64
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• 2015

In this paper, we propose a design of microwave motion detector using X-band doppler radar sensor to minimize the power consumption. To minimize the power consumption and implement battery operated system, pulse input with 2 KHz, 4% duty cycle is exerted on the doppler radar sensor. In order to simplify the process of working with ATmega2560 microcontroller unit, Arduino compatible board is designed and implemented. Arduino is open source hardware and many library software is published as open source tools. Smartphone app is also proposed and designed as a real-time user interface of the motion detector. The SQLite database on the Android mobile operating system is used for recording raw data of motion detection for post-processing job, such as fast Fourier transform (FFT). Bluetooth interface module is implemented on the motion detection board as a wireless communication interface to the smartphone. The speed of human movement is identified by post-processing FFT.

• Proceedings of the IEEK Conference
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• 2002.07b
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• pp.932-935
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• 2002

In this paper, we introduce new FTL(Flash Translation Layer) driver algorithm that tolerate the power off errors. FTL driver is the software that provide the block device interface to the upper layer software such as file systems or application programs that using the flash memory as a block device interfaced storage. Usually, the flash memory is used as the storage devices of the mobile system due to its low power consumption and small form factor. In mobile system, the state of the power supplement is not stable, because it using the small sized battery that has limited capacity. So, a sudden power off failure can be occurred when we read or write the data on the flash memory. During the write operation, power off failure may introduce the incomplete write operation. Incomplete write operation denotes the inconsistency of the data in flash memory. To provide the stable storage facility with flash memory in mobile system, FTL should provide the fault tolerance against the power off failure. SSR (Simple Sector Remapper) is a fault tolerant FTL driver that provides block device interface and also provides tolerance against power off errors.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.10a
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• pp.749-752
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• 2012

Recent social issues is energy issues, green computing has attracted attention. Active research on the power consumption of computer profiling is one of the various approaches for green computing. As a representative tool PowerAPI, PowerTop, JouleMeter, pTop, and EnergyChecker. These studies can be used to measure the power consumption of each computer device because it is based on a pure software. Based on this profiling process at the level of power consumption by performing the power consumption of each program can be analyzed. Therefore to identify the processes that consume a lot of power and control the total power consumption by reducing, also when designing the program, based on data profiling power enables the design of low-power programs, and ultimately can be oriented green computing. In this paper, by comparing and analyzing the associated representative studies, the ideal process level will draw on the characteristics of the power consumption profiler.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.4
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• pp.72-83
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• 2002

In this paper, a novel low-power VLSI system architecture was proposed. By exploiting software control of supply voltages, it simplifies hardware implementation, reduces power consumption efficiently, and avoids complicated interface circuits. The proposed architecture models clock frequency-supply voltage relationship by software modelling, enables individual control of supply voltages for all chips in the system, and restricts clock frequency to discrete levels of $f_{CLK}$, $f_{CLK}$2, $f_{CLK}$3... where $f_{CLK}$ is the master clock frequency A prototype system was implemented by modifying off-the-shelf microprocessor evaluation board and adding simple discrete devices such as level shifters and voltage switches. It was measured that the power consumption was reduced from 0.58W to 0.12W in the Prototype system. system.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.10a
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• pp.765-768
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• 2012

Recently, the supply ratio of smart devices application has become increasable, utilization of device increases constantly. At the same time, used application is more gentrified. However, using time of devices is decreased. To solve these problems, many research is studying about the hardware/software. One of them is profiling power consumption by process units. The process can be managed, based on measured energy consumption data. These means that it can efficiently use the residual energy. Application at the stage of program design can analyze and used-energy using the trace by considering the low-power can design. In this paper, we studied software-based power-metering framework for android platform. We survey each process-level power consumption measurement techniques, compare advantages and disadvantages of the technique and propose improved measures.