• Journal of KIISE:Software and Applications
• /
• v.29 no.1_2
• /
• pp.65-79
• /
• 2002

Object-oriented frameworks need to be systematically tested because they are reused in developing many applications software. They also need additional testing whenever they are extended for reuse. Frameworks, however, have properties that make it difficult to control and observe the testing of the parts that were modified and extended. In this paper, we describe the method of embedding test components as BIT(Built-In Test) into the framework's hot spots in order to efficiently detect the faults through testing that occurred while implementing application programs by modifying and extending the framework. The test components embedded into a framework make it easy to control and observe testing the framework, and thereby improve the testability of frameworks. Test components designed by the method proposed in this paper can be dynamically attached and detached to/from hot spots of a framework without changes or intervention to the framework code.

• The KIPS Transactions:PartD
• /
• v.9D no.5
• /
• pp.847-858
• /
• 2002

A purpose of the object-oriented programming is to promote reuse and development time, and to improve software quality. A way for this purpose is using a design information well-defined and tested in previous time when developing software. Such design information is called design patterns. The design patterns are descriptions of abstract solution to recurse software design problems In a systematic and general way. But because the design patterns are descriptions of abstract solution, the specification and application of patterns generally rely on manual implementation and is applied to various forms. As a result, we need to spend a lot of time to develop software program not only because of difficulty in analyzing and applying to patterns consistently, but also because of the frequent programing faults. And because the applied design patterns don't express inside application visually, it is difficult to analyze and test for this design patterns. In this paper, we propose automatic source code generating technique to be able to efficiently apply the element of design patterns when developing application. And we show a way to analyze and use the applied design patterns in application. As a result, the design patterns in application provide the consistent structure and efficiency, and make analysis and using effect increased.

• The Transactions of the Korean Institute of Electrical Engineers P
• /
• v.55 no.1
• /
• pp.6-12
• /
• 2006

A popular method used by primary protection for power transformer is current ratio differential relaying (RDR) with 2nd harmonic restraints. In modern power transformer due to the use of low-loss amorphous material, the 2nd harmonic component during inrush is significantly reduced. The higher the capacitance of the high voltage status and underground distribution, the more the differential current includes the 2nd harmonic component during internal fault. Thus the conventional method may not operate properly. This paper proposes an advanced relaying algorithm and the prototype IED hardware design and it's real-time experimental results. To evaluate performance of the proposed algorithm, the study is well constructed power system model including power transformer utilizing the EMTP software and the testing is made through simulation of various cases. The proposed relaying that is well constructed using DSP chip and microprocessor etc. has been developed and the prototype IED has been verified through on-line testing. The results show that an advanced relaying based prototype IED never mis-operated and correctly identified all the faults and that inrushes that are applied.

• Journal of the Korea Convergence Society
• /
• v.4 no.3
• /
• pp.21-26
• /
• 2013

Currently almost people use a personal computer for various purpose. But some people are not familiar to computer system. If they see only black screen on the monitor when they turn on the computer power, they can not recognize whether it is hardware or software faults. So, in this paper is aimed to develop the module of computer hardware fault detecter using ROM BIOS before OS booting. This module use PCI interface with mother board of computer. Before os booting, it can get the ROM BIOS memory by interrupt and show what hardware is fault according to the predefined memory content of BIOS.

• Journal of Electrical Engineering and Technology
• /
• v.6 no.4
• /
• pp.439-446
• /
• 2011

Frequency is an important operating parameter for the protection, control, and stability of a power system. Thus, it must be maintained very close to its nominal frequency. Due to the sudden change in generation and loads or faults in a power system, however, frequency deviates from its nominal value. An accurate monitoring of the power frequency is essential for optimum operation and prevention of wide area blackout. Most conventional frequency estimation schemes are based on the DFT filter. In these schemes, the gain error could cause defects when the frequency deviates from the nominal value. We present an advanced frequency estimation technique using gain compensation to enhance the DFT filter-based technique. The proposed technique can reduce the gain error caused when the frequency deviates from the nominal value. Simulation studies are performed using both the data from EMTP-RV software and the user-defined arbitrary signals to demonstrate the effectiveness of the proposed algorithm. Results show that the proposed algorithm achieves good performance under both steady state tests and dynamic conditions.

• The KIPS Transactions:PartA
• /
• v.15A no.3
• /
• pp.151-154
• /
• 2008

A middleware in grid computing environment is required to support seamless on-demand services over diverse resource situations in order to meet various user requirements [1]. Since grid computing applications need situation-aware middleware services in this environment. In this paper, we propose a semantic middleware architecture to support dynamic software component reconfiguration based fault and service ontology to provide fault-tolerance in a grid computing environment. Our middleware includes autonomic management to detect faults, analyze causes of them, and plan semantically meaningful strategies to recover from the failure using pre-defined fault and service ontology trees. We implemented a referenced prototype, Web-service based Application Execution Environment(Wapee), as a proof-of-concept, and showed the efficiency in runtime recovery.

• The Transactions of the Korean Institute of Electrical Engineers P
• /
• v.62 no.1
• /
• pp.12-17
• /
• 2013

Fault currents are expressed as a combination of harmonic components and exponentially decaying DC offset components, during the occurrence of fault in power system. The DC offset components are included, when the voltage phase angle of fault inception is closer to $0^{\circ}$ or $180^{\circ}$. The digital protection relay should be detected quickly and accurately during the faults, despite of the distortions of relaying signal by these components. It is very important to implement the robust protection algorithm, that is not affected by DC offset and harmonic components, because most relaying algorithms extract the fundamental frequency component from distorted relaying signal. So, In order to high performance in relaying, advanced DC offset removal filter is required. In this paper, a new DC offset removal filter, which is no need to preset a time constant of power system and accurately estimate the DC offset components with one cycle of data, is proposed, and compared with the other filter. In order to verify performance of the filter, we used collecting the current signals after synchronous machine modeling by ATPDraw5.7p4 software. The results of simulation, the proposed DC offset removal filter do not need any prior information, the phase delay and gain error were not occurred.

• Journal of the Korea Society of Computer and Information
• /
• v.21 no.10
• /
• pp.125-133
• /
• 2016

In this paper, we propose a real-time fault monitoring and dual system design of the countdown time-generating system, which is the main component of the mission control system. The countdown time-generating system produces a countdown signal that is distributed to mission control system devices. The stability of the countdown signal is essential for the main launch-related devices because they perform reserved functions based on the countdown time information received from the countdown time-generating system. Therefore, a reliable and fault-tolerant design is required for the countdown time-generating system. To ensure system reliability, component devices should be redundant and faults should be monitored in real time to manage the device changeover from Active mode to Standby mode upon fault detection. In addition, designing different methods for mode changeover based on fault classification is necessary for appropriate changeover. This study presents a real-time fault monitoring and changeover system, which is based on the dual system design of countdown time-generating devices, as well as experiment on real-time fault monitoring and changeover based on fault inputs.

• The Transactions of the Korean Institute of Electrical Engineers A
• /
• v.53 no.7
• /
• pp.365-374
• /
• 2004

The relay measures the frequency of the power system in order to detect faults and separate them from the system. Many estimation algorithms for the relay have been proposed to accurately measure the frequency. This paper proposes a new frequency measurement method using the digital phase locked-loop(DPLL) for the relay of the power system. The proposed method is configured with a DPLL scheme and verified through computer simulations and experimental tests. In order to cope with noises in the power system, filters are included in the input signal processing part and the frequency comparator. MATLAB is used for computer simulations and an experimental setup with a CPU and an FPGA(Field Programmable Gate Array) is constructed. The loop filter of the DPLL is run in the CPU software In adjust parameters and others are in the FPGA. Experimental tests are performed lot a function generator and the power system. Results show that the proposed method is appropriate to the frequency measurement for the relay.

• Nuclear Engineering and Technology
• /
• v.45 no.6
• /
• pp.795-802
• /
• 2013

For the improvement of APR1400 Diverse Protection System (DPS) design, the Advanced DPS (ADPS) has recently been developed to enhance the fault tolerance capability of the system. Major fault masking features of the ADPS compared with the APR1400 DPS are the changes to the channel configuration and reactor trip actuation equipment. To minimize the fault occurrences within the ADPS, and to mitigate the consequences of common-cause failures (CCF) within the safety I&C systems, several fault avoidance design features have been applied in the ADPS. The fault avoidance design features include the changes to the system software classification, communication methods, equipment platform, MMI equipment, etc. In addition, the fault detection, location, containment, and recovery processes have been incorporated in the ADPS design. Therefore, it is expected that the ADPS can provide an enhanced fault tolerance capability against the possible faults within the system and its input/output equipment, and the CCF of safety systems.