• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.9C
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• pp.734-742
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• 2008

In spatially multiplexed MIMO systems that enable high data rate transmission over wireless communication channels, the spatial demultiplexing at the receiver is a challenging task and various demultiplexing methods have been developed. Among the previous methods, maximum likelihood detection with QR decomposition and M-algorithm (QRM-MLD), sphere decoding (SD), QOC, and MOC schemes have been reported to achieve a (near) maximum likelihood (ML) hard decision performance. In general, however, the reliability of soft output of these schemes is not satisfactory. In this paper, we propose a method which enhances the reliability of soft output. By computer simulations, we demonstrate the improved performance by the proposed method.

• Journal of Communications and Networks
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• v.13 no.3
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• pp.257-265
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• 2011

In this paper, a cooperative relaying protocol called soft-decision-and-forward (SDF) with multiple antennas in each node is introduced. SDF protocol exploits the soft decision source symbol values from the received signal at the relay node. For orthogonal transmission (OT), orthogonal codes including Alamouti code are used and for non-orthogonal transmission (NT), distributed space-time codes are designed by using a quasi-orthogonal space-time block code. The optimal maximum likelihood (ML) decoders for the proposed protocol with low decoding complexity are proposed. For OT, the ML decoders are derived as symbolwise decoders while for NT, the ML decoders are derived as pairwise decoders. It can be seen through simulations that SDF protocol outperforms AF protocol for both OT and NT.

• Proceedings of the IEEK Conference
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• 1999.06a
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• pp.61-64
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• 1999

The turbo code appropriate to IMT-2000 is known to have a good performance whenever the size of frame increases. But it is not appropriate to a sort of video service to need real time because of decoding complexity and long delay time by the size of frame. Therefore this paper proposes decoding decision algorithm of short frame in which soft output is weighted according to iteration number in turbo decoder. Performance of the proposed algorithm is analysed in the AWGN channel when short length of frame is 100, 256, 640. As the result. it is appeared that the proposed decoding decision algorithm has improved in BER other than in the existing MAP decoding algorithm.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.10 no.3
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• pp.1131-1143
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• 2016

Differential detection schemes do not require any channel estimation, which can be employed under user mobility with low computational complexity. In this work, a soft-input soft-output (SISO) differential detection algorithm is proposed for amplify-and-forward (AF) over time-varying relaying channels based cooperative communications system. Furthermore, maximum-likelihood (ML) detector for M-ary differential Phase-shift keying (DPSK) is derived to calculate a posteriori probabilities (APP) of information bits. In addition, when the SISO is exploited in conjunction with channel decoding, iterative detection and decoding approach by exchanging extrinsic information with outer code is obtained. Finally, simulation results show that the proposed non-coherent approach improves detection performance significantly. In particular, the system can obtain greater performance gain under fast-fading channels.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.4
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• pp.488-496
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• 2016

This paper presents a low-complexity non-iterative soft-decision Bose-Chaudhuri-Hocquenghem (SD-BCH) decoder architecture and design technique for wireless body area networks (WBANs). A SD-BCH decoder with test syndrome computation, a syndrome calculator, Chien search and metric check, and error location decision is proposed. The proposed SD-BCH decoder not only uses test syndromes, but also does not have an iteration process. The proposed SD-BCH decoder provides a 0.75~1 dB coding gain compared to a hard-decision BCH (HD-BCH) decoder, and almost similar coding gain compared to a conventional SD-BCH decoder. The proposed SD-BCH (63, 51) decoder was designed and implemented using 90-nm CMOS standard cell technology. Synthesis results show that the proposed non-iterative SD-BCH decoder using a serial structure can lead to a 75% reduction in hardware complexity and a clock speed 3.8 times faster than a conventional SD-BCH decoder.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2013.10a
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• pp.399-401
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• 2013

In this paper, we present the method to impove the performance by using iterative decoding in LDPC codes with 8-PSK modulation. Iterative decoding is the technique that improve the performance after the input signals of receiver are re-calculated by using the soft decision output of decoder. DVB-S2 system with 8-PSK modulation based on iterative decoding had a better performance than DVB-S2 with 8-PSK modulation over Gaussian channels.

• The Journal of the Convergence on Culture Technology
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• v.7 no.3
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• pp.565-570
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• 2021

A soft-decision decoding scheme of a channel code for correcting an error occurring in a receiver of a digital communication systems is proposed. A method for efficiently decoding by use of the linear and arithmetic structure of linear block codes is presented. In this way, the probability of decoding errors has been reduced. In addition, it is possible to reduce the complexity of decoding as well. Sufficient conditions for achieving optimal decoding has been derived. As a result, the sufficient conditions enable efficient search for candidate codewords. With the proposed decoding scheme, we can effectively perform the decoding while lowering the block error probability.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.11
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• pp.54-64
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• 2010

Reed-Solomon (RS) codes are the most widely used error correcting codes in digital communications and data storage. Recently, Sudan found algorithm of list decoder for RS codes. List decoder has larger decoding radius than conventional hard-decision decoding algorithms and return more than one candidate polynomial. But, the algorithm includes interpolation and factorization step that demand massive computations. In this paper, an efficient architecture and processing schedule are proposed. The architecture consists of R-MAC, memories, and control unit. The R-MAC computes both of RC and PU steps that are main part of the factorization algorithm. The proposed architecture can achieve higher hardware utilization efficiency (HUE) and throughput by using efficient processing schedule and memory architecture. Also, the architecture can be designed flexibly with scalability for various applications. We design and synthesize our architecture using Dongbu-Anam $0.18{\mu}m$ standard cell library and the maximum clock frequency is 330MHz.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.7
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• pp.1419-1426
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• 1997

A new SCEE(Syndrome Check Error Estimation) decoding method for convolutional code and concatenated SCEE/RS (Reed-Solomon) conding scheme are proposed. First, we describe the operation of the decoding steps in the proposed algorithm. Then deterministic values on the decoding operation are drived when some combination of predecoder-reencoder is used. Computer simulation results show that the compuatational complexity of the proposed SCEE decoder is significantly reduced compared to that of conventional Viterbi-decoder without degratation of the $P_{e}$ performance. Also, the concatenated SCEE/RS decoder has almost the same complexity of a RS decoder and its coding gain is higher than that of soft decision Viterbi or RS decoder respectively.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.3
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• pp.59-67
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• 2013

Reed-Solomon (RS) codes are powerful error-correcting codes used in diverse applications. Recently, algebraic soft-decision decoding algorithm for RS codes that can correct the errors beyond the error correcting bound has been proposed. The algorithm requires very intensive computations for interpolation, therefore an efficient VLSI architecture, which is realizable in hardware with a moderate hardware complexity, is mandatory for various applications. In this paper, we propose an efficient architecture with low hardware complexity for interpolation in soft-decision list decoding of Reed-Solomon codes. The proposed architecture processes the candidate polynomial in such a way that the terms of X degrees are processed in serial and the terms of Y degrees are processed in parallel. The processing order of candidate polynomials adaptively changes to increase the efficiency of memory access for coefficients; this minimizes the internal registers and the number of memory accesses and simplifies the memory structure by combining and storing data in memory. Also, the proposed architecture shows high hardware efficiency, since each module is balanced in terms of latency and the modules are maximally overlapped in schedule. The proposed interpolation architecture for the (255, 239) RS list decoder is designed and synthesized using the DongbuHitek $0.18{\mu}m$ standard cell library, the number of gate counts is 25.1K and the maximum operating frequency is 200 MHz.