• KSII Transactions on Internet and Information Systems (TIIS)
• /
• 제9권7호
• /
• pp.2614-2632
• /
• 2015

A multiple symbol detection (MSD) algorithm is proposed relying on soft information for ultra-wideband systems, where differential space-time block code is employed. The proposed algorithm aims to calculate a posteriori probabilities (APP) of information symbols, where a forward and backward message passing mechanism is implemented based on the BCJR algorithm. Specifically, an MSD metric is analyzed and performed for serving the APP model. Furthermore, an autocorrelation sampling is employed to exploit signals dependencies among different symbols, where the observation window slides one symbol each time. With the aid of the bidirectional message passing mechanism and the proposed sampling approach, the proposed MSD algorithm achieves a better detection performance as compared with the existing MSD. In addition, when the proposed MSD is exploited in conjunction with channel decoding, an iterative soft-input soft-output MSD approach is obtained. Finally, simulations demonstrate that the proposed approaches improve detection performance significantly.

• 한국산학기술학회논문지
• /
• 제15권11호
• /
• pp.6838-6844
• /
• 2014

LTE-A 시스템은 고속 데이터 전송을 위해 다중안테나를 장착하고 있다. 일반적으로 공간다중화 다중안테나 시스템의 수신기 복잡도는 후보벡터의 개수에 따라 증가한다. 후보벡터의 개수가 증가함에 따라 연판정 값의 신뢰도가 향상된다. 많은 수의 후보벡터를 생성하는 최우도 신호검출방식을 사용하면 우수한 성능을 달성할 수 있다. 반면 적은 개수의 후보벡터를 생성하는 저복잡도 수신기는 신뢰도가 낮은 연판정 값을 생성한다. 본 논문에서는 적은 수의 후보벡터를 사용해서 얻게되는 연판정 값의 신뢰도를 향상시키는 새로운 기술을 제안하고 모의실험을 통해 개선된 성능을 확인한다.

• Journal of Power Electronics
• /
• 제13권1호
• /
• pp.20-30
• /
• 2013

This paper presents a soft switching DC/DC converter for high voltage application. The interleaved pulse-width modulation (PWM) scheme is used to reduce the ripple current at the output capacitor and the size of output inductors. Two converter cells are connected in series at the high voltage side to reduce the voltage stresses of the active switches. Thus, the voltage stress of each switch is clamped at one half of the input voltage. On the other hand, the output sides of two converter cells are connected in parallel to achieve the load current sharing and reduce the current stress of output inductors. In each converter cell, a half-bridge converter with the asymmetrical PWM scheme is adopted to control power switches and to regulate the output voltage at a desired voltage level. Based on the resonant behavior by the output capacitance of power switches and the transformer leakage inductance, active switches can be turned on at zero voltage switching (ZVS) during the transition interval. Thus, the switching losses of power MOSFETs are reduced. The current doubler rectifier is used at the secondary side to partially cancel ripple current. Therefore, the root-mean-square (rms) current at output capacitor is reduced. The proposed converter can be applied for high input voltage applications such as a three-phase 380V utility system. Finally, experiments based on a laboratory prototype with 960W (24V/40A) rated power are provided to demonstrate the performance of proposed converter.

• 한국산업정보학회:학술대회논문집
• /
• 한국산업정보학회 1999년도 추계공동학술대회 논문집:21세기지식경영과 정보기술
• /
• pp.693-700
• /
• 1999

The Servo motor is consistent with the magnet rotor, winding, magnetic back iron and the sensor. Especially the soft magnetic back iron in the servo motor, which consists of the magnet rotor and winding, and between these two components lies the magnetic circle. Its important to monitor the output power of to make conclusive decision for designs. In these days main household electrical appliances, business machinery and tools are made by process of miniaturization. Because of this miniaturization in hardware, miniaturization of the servo motor is essential But the decrease inside affects the power output. For improve of these has been several attempt at improving the power output of these smaller servo motors. There has been experiment in the servo motor composition, composing of the improvement of the soft magnetic back iron through comparison of the out put power plans are being made.

• 한국전기전자재료학회논문지
• /
• 제21권2호
• /
• pp.104-110
• /
• 2008

In this paper we proposed a new source-drain structure for N-type MOSFET which can suppress the output resistance reduction of a device in saturation region due to soft break down leakage at high drain voltage when the gate is biased around relatively low voltage. When a device is generally used as a switch at high gate bias the current level is very important for the operation. but in electronic circuit like an amplifier we should mainly consider the output resistance for the stable voltage gain and the operation at low gate bias. Hence with T-SUPREM simulator we designed devices that operate at low gate bias and high gate bias respectively without a extra photo mask layer and ion-implantation steps. As a result the soft break down leakage due to impact ionization is reduced remarkably and the output resistance increases about 3 times in the device that operates at the low gate bias. Also it is expected that electronic circuit designers can easily design a circuit using the offered N-type MOSFET device with the better output resistance.

• 한국통신학회논문지
• /
• 제34권6C호
• /
• pp.634-641
• /
• 2009

공간적으로 다중화된 다중 안테나 시스템에서 OSIC계열의 신호검출 기법은 실현 가능한 연산 복잡도를 가지며 ML성능에 도달하기 위해 지속적으로 발전해 왔다. 하지만 지금까지 제안된 다양한 OSIC 기반의 준 최적 신호검출 기법들은 특정 비트의 연 판정 값을 계산하는 과정에서 공 벡터 문제가 발생하여 상당한 연 판정 성능 저하를 보인다. 이러한 문제를 해결하기 위해 다양한 해결 방안이 제안되었지만 연 판정 ML성능에 도달하지 못하거나, 도달하기 위해서는 많은 후보 벡터들이 필요하다. 본 논문에서는 복수개의 재 정렬된 채널 행렬과 각 채널 행렬의 QR분해 시 존재하는 상 삼각 행렬의 구조를 효율적으로 이용하는 이중 검출을 바탕으로 공 벡터 문제를 효과적으로 차단하며 경 판정 ML성능뿐만 아니라 연 판정 ML성능에 근접하는 신호 검출 기법을 제안한다. 성능과 연산 복잡도 관점에서 제안된 검출기법은 기존의 제안된 준 최적 검출기법 보다 동일한 성능에서 더 적은 연산 복잡도를 가지거나, 증가된 복잡도 만큼 더 우수한 연 판정 성능을 보임을 확인할 수 있다.

• 한국통신학회논문지
• /
• 제35권11C호
• /
• pp.896-900
• /
• 2010

본 논문은 차세대 저장장치로 각광받고 있는 패턴드 미디어 장치에 대한 트랙 위치 오프셋에 따른 성능을 알아본다. 패턴드 미디어 채널은 SUL(Soft Underlayer)의 유무에 따라 1차원 검출기인 비터비 검출기와 2차원 검출기인 2차원 SOVA(Soft output Viterbi algorithm)를 이용해 실험하였고, 트랙 위치 오프셋이 없을 때, 10%, 20%, 30%, 40% 있을 때 실험하였다. 트랙 위치 오프셋이 10%일 때는 성능영화가 0.3 dB ~ 0.5 dB 정도로 크지 않았지만 그 이상이 되면, 성능열화가 심해지는 것을 볼 수 있다.

• KSII Transactions on Internet and Information Systems (TIIS)
• /
• 제10권3호
• /
• pp.1131-1143
• /
• 2016

Differential detection schemes do not require any channel estimation, which can be employed under user mobility with low computational complexity. In this work, a soft-input soft-output (SISO) differential detection algorithm is proposed for amplify-and-forward (AF) over time-varying relaying channels based cooperative communications system. Furthermore, maximum-likelihood (ML) detector for M-ary differential Phase-shift keying (DPSK) is derived to calculate a posteriori probabilities (APP) of information bits. In addition, when the SISO is exploited in conjunction with channel decoding, iterative detection and decoding approach by exchanging extrinsic information with outer code is obtained. Finally, simulation results show that the proposed non-coherent approach improves detection performance significantly. In particular, the system can obtain greater performance gain under fast-fading channels.

• 한국통신학회논문지
• /
• 제35권12C호
• /
• pp.1044-1051
• /
• 2010

본 논문에서는 공간다중화 multiple input multiple output (MIMO) 시스템을 위한 효율적인 soft-output 신호검출 기법을 제안한다. 제안된 기법은 ordered successive interference cancellation (OSIC) 알고리즘을 기반으로 하지만, 오류 전파 문제를 크게 줄임으로써 기존 OSIC 알고리즘에 비해 큰 성능 향상을 보인다. 제안된 기법은 다중 순서화 기술을 이용한 enhanced OSIC (ESIC) 알고리즘을 결합한 기법으로 신뢰도 높은 log likelihood ratio(LLR) 값을 매우 적은 후보 심볼 벡터를 이용하여 생성할 수 있다. 본 논문에서는 $4{\times}4$ 16-QAM MIMO 시스템을 위한 OSIC, K-Best 가법과 제안된 신호검출 기법을 $0.13{\mu}m$ CMOS 기술 환경에서 구현하였으며, 모의 시험과 구현 결과를 통해 제안된 신호검출 기법이 성능과 하드웨어 구현 측면에서 매우 효율적임을 확인하였다.

• 한국통신학회논문지
• /
• 제39A권3호
• /
• pp.121-126
• /
• 2014

Demand of the data storage becomes more and more growing. This requests the next generation of storage devices to have the dominated storage capability associated with superfast read/write rate. Holographic data storage (HDS) is investigated for a long time and is considered to be a candidate for the future storage system. However, it has two-dimensional intersymbol interference that conventional one-dimensional detection solutions have not yet handled strictly because of the complexity level of system as well as the cost. We propose a new scheme that combines iterative soft output Viterbi algorithm with noise filter for improving the bit error rate performance of HDS.