• Title/Summary/Keyword: Soft fault

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Development of Automatic Fault Detection System for Chip-On-Film (칩 온 필름을 위한 자동 결함 검출 시스템 개발)

  • Ryu, Jee-Youl;Noh, Seok-Ho
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.16 no.2
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    • pp.313-318
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    • 2012
  • This paper presents an automatic system to detect variety of faults from fine pitch COF(chip-on-film) which is less than $30{\mu}m$. Developed system contains circuits and technique to detect fast various faults such as hard open, hard short, soft open and soft short from fine pattern. Basic principle for fault detection is to monitor fine differential voltage from pattern resistance differences between fault-free and faulty cases. The technique uses also radio frequency resonator arrays for easy detection to amplify fine differential voltage. We anticipate that proposed system is to be an alternative for conventional COF test systems since it can fast and accurately detect variety of faults from fine pattern COF test process.

Simulated Fault Injection Using Simulator Modification Technique

  • Na, Jong-Whoa;Lee, Dong-Woo
    • ETRI Journal
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    • v.33 no.1
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    • pp.50-59
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    • 2011
  • In the current very deep submicron technology era, fault tolerant mechanisms perform an essential function to cope with the effects of soft errors. To evaluate the effectiveness of the fault tolerant mechanism, reliability engineers use simulated fault injections using either saboteur modules or mutants in the simulation model. However, the two methods suffer from both inefficiency in the simulation mechanism and difficulties with the experimental setups. To overcome these inefficiencies, we propose the Verilog-based simulated fault injection (VFI) technique. VFI has the following advantages. First, modification of the design model is unnecessary. Second, the fault injection simulation procedure is simple and efficient. Third, various types of fault injection experiments can be performed. To evaluate the effectiveness of the proposed methodology, we developed a VFI environment using the ICARUS Verilog Simulator. From the experimental results, we were able to qualitatively evaluate the reliability of the target simulation models and to assess the effectiveness of the employed fault-tolerance mechanisms.

Integrating Fuzzy based Fault diagnosis with Constrained Model Predictive Control for Industrial Applications

  • Mani, Geetha;Sivaraman, Natarajan
    • Journal of Electrical Engineering and Technology
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    • v.12 no.2
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    • pp.886-889
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    • 2017
  • An active Fault Tolerant Model Predictive Control (FTMPC) using Fuzzy scheduler is developed. Fault tolerant Control (FTC) system stages are broadly classified into two namely Fault Detection and Isolation (FDI) and fault accommodation. Basically, the faults are identified by means of state estimation techniques. Then using the decision based approach it is isolated. This is usually performed using soft computing techniques. Fuzzy Decision Making (FDM) system classifies the faults. After identification and classification of the faults, the model is selected by using the information obtained from FDI. Then this model is fed into FTC in the form of MPC scheme by Takagi-Sugeno Fuzzy scheduler. The Fault tolerance is performed by switching the appropriate model for each identified faults. Thus by incorporating the fuzzy scheduled based FTC it becomes more efficient. The system will be thereafter able to detect the faults, isolate it and also able to accommodate the faults in the sensors and actuators of the Continuous Stirred Tank Reactor (CSTR) process while the conventional MPC does not have the ability to perform it.

Single Parameter Fault Identification Technique for DC Motor through Wavelet Analysis and Fuzzy Logic

  • Winston, D.Prince;Saravanan, M.
    • Journal of Electrical Engineering and Technology
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    • v.8 no.5
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    • pp.1049-1055
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    • 2013
  • DC motors are widely used in industries like cement, paper manufacturing, etc., even today. Early fault identification in dc motors significantly improves its life time and reduces power consumption. Many conventional and soft computing techniques for fault identification in DC motors including a recent work using model based analysis with the help of fuzzy logic are available in literature. In this paper fuzzy logic and norm based wavelet analysis of startup transient current are proposed to identify and quantify the armature winding fault and bearing fault in DC motors, respectively. Results obtained by simulation using Matlab and Simulink are presented in this paper to validate the proposed work.

Seismic Performance of Bridge with Pile Bent Structures in Soft Ground against Near-Fault Ground Motions (연약지반에 건설된 단일형 현장타설말뚝 교량의 근단층지반운동에 대한 내진성능)

  • Sun, Chang-Ho;An, Sung-Min;Kim, Jung-Han;Kim, Ick-Hyun
    • Journal of the Korea institute for structural maintenance and inspection
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    • v.23 no.7
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    • pp.137-144
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    • 2019
  • For the structures near the seismogenic fault, the evaluation of seismic performance against near-fault ground motions is important as well as for design ground motions. In this study, characteristics of seismic behaviors and seismic performance of the pile-bent bridge constructed on the thick soft soil site with various weak soil layers were analyzed. The input ground motions were synthesized by the directivity pulse parameters for intra-plate regions. The ground motion acceleration histories of each layer were obtained by one-dimensional site response analysis. Each soil layer was modeled by equivalent linear springs, and multi-support excitations with different input ground motions at each soil spring were applied for nonlinear seismic analyses. The analysis result by the near-fault ground motions and ground motions matched to design spectra were compared. In case of the near fault ground motion input, the bridge behaved within the elastic range but the location of the maximum moment occurred was different from the result of design ground motion input.

Reliability Analysis of Interleaved Memory with a Scrubbing Technique (인터리빙 구조를 갖는 메모리의 스크러빙 기법 적용에 따른 신뢰도 해석)

  • Ryu, Sang-Moon
    • Journal of Institute of Control, Robotics and Systems
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    • v.20 no.4
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    • pp.443-448
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    • 2014
  • Soft errors in memory devices that caused by radiation are the main threat from a reliability point of view. This threat can be commonly overcome with the combination of SEC (Single-Error Correction) codes and scrubbing technique. The interleaving architecture can give memory devices the ability of tolerating these soft errors, especially against multiple-bit soft errors. And the interleaving distance plays a key role in building the tolerance against multiple-bit soft errors. This paper proposes a reliability model of an interleaved memory device which suffers from multiple-bit soft errors and are protected by a combination of SEC code and scrubbing. The proposed model shows how the interleaving distance works to improve the reliability and can be used to make a decision in determining optimal scrubbing technique to meet the demands in reliability.

Decision Making on Bus Splitting Locations Using a Modified Fault Current Constrained Optimal Power Flow (FCC-OPF)

  • Song, Hwachang;Vovos, Panagis N.;Cho, Kang-Wook;Kim, Tae-Sun
    • Journal of Electrical Engineering and Technology
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    • v.11 no.1
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    • pp.76-85
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    • 2016
  • This paper presents a method of decision on where bus splitting is needed to reduce fault current level of power systems and to satisfy the fault current constraints. The method employs a modified fault current constrained optimal power flow (FCC-OPF) with X variables for the candidate locations of splitting and for decision making on whether to split or not, it adopts soft-discretization by augmenting inversed U-shaped penalty terms. Also, this paper discusses the procedure on the adequate selection of bus splitting locations based on the results of the modified FCC-OPF, to reduce the total number of the actions taken.

Testing of CMOS Operational Amplifier Using Offset Voltage (오프셋 전압을 이용한 CMOS 연산증폭기의 테스팅)

  • Song, Geun-Ho;Kim, Gang-Cheol;Han, Seok-Bung
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.38 no.1
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    • pp.44-54
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    • 2001
  • In this paper, a novel test method is proposed to detect the hard and soft fault in analog circuits. The proposed test method makes use of the offset voltage, which is one of the op-amps characteristics. During the test mode, CUT is modified to unit gain op-amps with feedback loop. When the input of the op-amp is grounded, a good circuit has a small offset voltage, but a faulty circuit has a large offset voltage. Faults in the op-amp which cause the offset voltage exceeding predefined range of tolerance can be detected. In the proposed method, no test vector is required to be applied. Therefore the test vector generation problem is eliminated and the test time and cost is reduced. In this note, the validity of the proposed test method has been verified through the example of the dual slope A/D converter. The HSPICE simulations results affirm that the presented method assures a high fault coverage.

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Failure probability of tall buildings with TMD in the presence of structural, seismic, and soil uncertainties

  • Sadegh, Etedali;Mohammad, Seifi;Morteza, Akbari
    • Structural Engineering and Mechanics
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    • v.85 no.3
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    • pp.381-391
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    • 2023
  • The seismic performance of the tall building equipped with a tuned mass damper (TMD) considering soil-structure interaction (SSI) effects is well studied in the literature. However, these studies are performed on the nominal model of the seismic-excited structural system with SSI. Hence, the outcomes of the studies may not valid for the actual structural system. To address the study gap, the reliability theory as a useful and powerful method is utilized in the paper. The present study aims to carry out reliability analyses on tall buildings equipped with TMD under near-field pulse-like (NFPL) ground motions considering SSI effects using a subset simulation (SS) method. In the presence of uncertainties of the structural model, TMD device, foundation, soil, and near-field pulse-like ground motions, the numerical studies are performed on a benchmark 40-story building and the failure probabilities of the structures with and without TMD are evaluated. Three types of soils (dense, medium, and soft soils), different earthquake magnitudes (Mw = 7,0. 7,25. 7,5 ), different nearest fault distances (r = 5. 10 and 15 km), and three seismic performance levels of immediate occupancy (IO), life safety (LS), and collapse prevention (CP) are considered in this study. The results show that tall buildings built near faults and on soft soils are more affected by uncertainties of the structural and ground motion models. Hence, ignoring these uncertainties may result in an inaccurate estimation of the maximum seismic responses. Also, it is found the TMD is not able to reduce the failure probabilities of the structure in the IO seismic performance level, especially for high earthquake magnitudes and structures built near the fault. However, TMD is significantly effective in the reduction of failure probability for the LS and CP performance levels. For weak earthquakes and long fault distances, the failure probabilities of both structures with and without TMD are near zero, and the efficiency of the TMD in the reduction of failure probabilities is reduced by increasing earthquake magnitudes and the reduction of fault distance. As soil softness increases, the failure probability of structures both with and without TMD often increases, especially for severe near-fault earthquake motion.

The Optimized Monolithic Fault Protection Circuit for the Soft-shutdown behavior of 600V PT-IGBT by employing a New Blanking Filter (600V Punch-through형 절연 게이트 바이폴라 트랜지스터의 Soft-shutdown을 위해 시간 지연 회로를 적용한 새로운 보호회로)

  • Lim, Ji-Yong;Ji, In-Hwan;Ha, Min-Woo;Choi, Young-Hwan;Choi, Yearn-Ik;Han, Min-Koo
    • Proceedings of the KIEE Conference
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    • 2006.07c
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    • pp.1299-1300
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    • 2006
  • Floating p-well 전압 감지를 이용한 시간 지연 회로를 적용하여 punch-though형 절연 게이트 바이폴라 트랜지스터 (PT-IGBT)의 최적화된 보호 회로를 제안하였다. Floating P-well 축전기와 게이트 저항은 정상 스위칭 동작시 단락 회로 감지 동작 (false detection of fault)을 차단하며, floating p-well 전압은 단락회로 상황시 풀-다운 (pull-down) MOSFET의 문턱 전압 이상으로 상승되어 풀-다운 MOSFET을 턴-온(turn-on) 시킴으로서 IGBT의 게이트 전압을 감소시킨다. 이에 따라 IGBT의 컬렉터 전류는 자연스럽게 감소된다. 실험 결과를 통해, 단락회로 상황에서 최적화된 IGBT의 보호회로가 소프트-셧다운 (soft-shutdown) 특성을 보이는 것을 확인할 수 있다.

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