• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.38C no.6
• /
• pp.540-549
• /
• 2013

An adaptive non-uniform quantization scheme is proposed for soft-decision error correction in NAND flash memory. Even though the conventional maximizing mutual information (MMI) quantizer shows the optimal post-FEC (forward error correction) bit error rate (BER) performance, this quantization scheme demands heavy computational overheads due to the exhaustive search to find the optimal parameter values. The proposed quantization scheme has a simple structure that is constructed by only six parameters, and the optimal values of them are found by maximizing the mutual information between the input and the output symbols. It is demonstrated that the proposed quantization scheme improves the BER performance of soft-decision decoding with only small computational overheads.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.26 no.11A
• /
• pp.1803-1811
• /
• 2001

In this paper, Forward Error Correction(FEC) that is satisfied with ITU-T Recommendation J.83, Annex B(North American Data Over Cable Service Interface Specifications(DOCSIS) for Multimedia Cable Network System(MCNS)) is analyzed. The FEC consist of Reed-Solomon(RS) layer, interleaving layer, randomization layer, and trellis coded modulation(TCM) layer. The effects of quantization of input symbol and of trace-back depth in the Viterbi decoder are simulated over AWGN channels.

• Journal of the Korean Institute of Intelligent Systems
• /
• v.18 no.5
• /
• pp.611-616
• /
• 2008

Error correcting codes (ECCs) are commonly used to protect against the soft errors. Single error correcting and double error detecting (SEC-DED) codes are generally used for this purpose. The proposed approach in this paper selectively reduced power consumption, delay, and area in single-error correcting, double error-detecting checker circuits that perform memory error correction. The multi-objective genetic algorithm is employed to solve the non -linear optimization problem. The proposed method allows that user can choose one of different non-dominated solutions depending on which consideration is important among them. Because we use multi-objective genetic algorithm, we can find various dominated solutions. Therefore, we can choose the ECC according to the important factor of the power, delay and area. The method is applied to odd-column weight Hsiao code which is well- known ECC code and experiments were performed to show the performance of the proposed method.

• Asia-pacific Journal of Multimedia Services Convergent with Art, Humanities, and Sociology
• /
• v.4 no.2
• /
• pp.369-378
• /
• 2014

The Reed-Muller code is one of the efficient algorithms for multiple bit error correction, however, its high-computation requirement inherent in the decoding process prohibits its use in practical applications. To solve this problem, this paper proposes a graphics processing unit (GPU)-based parallel error control approach using Reed-Muller R(r, m) coding for real-time wireless communication systems. GPU offers a high-throughput parallel computing platform that can achieve the desired high-performance decoding by exploiting massive parallelism inherent in the algorithm. In addition, we compare the performance of the GPU-based approach with the equivalent sequential approach that runs on the traditional CPU. The experimental results indicate that the proposed GPU-based approach exceedingly outperforms the sequential approach in terms of execution time, yielding over 70× speedup.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.35 no.6B
• /
• pp.948-953
• /
• 2010

In this paper, we propose multi-bit soft error detection method which can use an instruction cache of superscalar CPU architecture. Proposed method is applied to high-speed static RAM for instruction cache. Using 1D parity and interleaving, it has less memory overhead and detects more multi-bit errors comparing with other methods. It only detects occurrence of soft errors in static RAM. Error correction is treated like a cache miss situation. When soft errors are occurred, it is detected by 1D parity. Instruction cache just fetch the words from lower-level memory to correct errors. This method can detect multi-bit errors in maximum 4$\times$4 window.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.46 no.1
• /
• pp.15-23
• /
• 2009

Microprocessors, which need correct arithmetic operations, have been the subject of in-depth research in relation to soft errors. Of the existing microprocessor devices, the memory cell is the most vulnerable to soft errors. Moreover, when soft errors emerge in a memory cell, the processes and operations are greatly affected because the memory cell contains important information and instructions about the entire process or operation. Users do not realize that if soft errors go undetected, arithmetic operations and processes will have unexpected outcomes. In the field of architectural design, the tool that is commonly used to detect and correct soft errors is the error check and correction code. The Itanium, IBM PowerPC G5 microprocessors contain Hamming and Rasio codes in their level-2 cache. This research, however, focuses on huge server devices and does not consider power consumption. As the operating and threshold voltage is currently shrinking with the emergence of high-density and low-power embedded microprocessors, there is an urgent need to develop ECC (error check correction) circuits. In this study, the in-output data of the level-2 cache were analyzed using SimpleScalar-ARM, and a 32-bit H-matrix for the level-2 cache of an embedded microprocessor is proposed. From the point of view of power consumption, the proposed H-matrix can be implemented using a schematic editor of Cadence. Therefore, it is comparable to the modified Hamming code, which uses H-spice. The MiBench program and TSMC 0.18 um were used in this study for verification purposes.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.39A no.3
• /
• pp.127-139
• /
• 2014

In this paper, we present two signal processing techniques for designing binary error correction codes for Multi-Level Cell(MLC) NAND flash memory. MLC NAND flash memory saves the non-binary symbol at each cell and shows asymmetric channel LLR l-density which makes it difficult to design soft-decision binary error correction codes such as LDPC codes and Polar codes. Therefore, we apply density mirroring and EM algorithm for approximating the MLC NAND flash memory channel to the binary-input memoryless channel. The density mirroring processes channel LLRs to satisfy roughly all-zero codeword assumption, and then EM algorithm is applied to l-density after density mirroring for approximating it to mixture of symmetric Gaussian densities. These two signal processing techniques make it possible to use conventional code design algorithms, such as density evolution and EXIT chart, for MLC NAND flash memory channel.

• Proceedings of the KIEE Conference
• /
• 1999.07g
• /
• pp.3199-3201
• /
• 1999

Convolutional coding with Viterbi decoding is known as a powerful method for forward error correction among many kinds of channel coding methods. This paper presents a soft decision Viterbi decoder which has systolic array trace-back architecture[1]. Soft decision is known as more effective method than hard decision and most of digital communication systems use soft decision. The advantage of using a systolic array decoder is that the trace-back operation can be accomplished continuously in an array of registers in a pipe-line fashion, instead of waiting for the entire trace-back procedure to be completed at each iteration. Therefore it may be suitable for faster communication system. We described operations of each module of the decoder and showed results of the logic synthesis and functional simulation.

• Progress in Medical Physics
• /
• v.28 no.4
• /
• pp.207-217
• /
• 2017

For effective patient treatment in proton therapy, it is therefore important to accurately measure the beam range. For measuring beam range, various researchers determine the beam range by measuring the prompt gammas generated during nuclear reactions of protons with materials. However, the accuracy of the beam range determination can be lowered in heterogeneous phantoms, because of the differences with respect to the prompt gamma production depending on the properties of the material. In this research, to improve the beam range determination in a heterogeneous phantom, we derived a formula to correct the prompt-gamma distribution using the ratio of the prompt gamma production, stopping power, and density obtained for each material. Then, the prompt-gamma distributions were acquired by a multi-slit prompt-gamma camera on various kinds of heterogeneous phantoms using a Geant4 Monte Carlo simulation, and the deduced formula was applied to the prompt-gamma distributions. For the case involving the phantom having bone-equivalent material in the soft tissue-equivalent material, it was confirmed that compared to the actual range, the determined ranges were relatively accurate both before and after correction. In the case of a phantom having the lung-equivalent material in the soft tissue-equivalent material, although the maximum error before correction was 18.7 mm, the difference was very large. However, when the correction method was applied, the accuracy was significantly improved by a maximum error of 4.1 mm. Moreover, for a phantom that was constructed based on CT data, after applying the calibration method, the beam range could be generally determined within an error of 2.5 mm. Simulation results confirmed the potential to determine the beam range with high accuracy in heterogeneous phantoms by applying the proposed correction method. In future, these methods will be verified by performing experiments using a therapeutic proton beam.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2011.10a
• /
• pp.701-704
• /
• 2011

The reliability of a computer system largely depends on that of its memory systems, which are vulnerable to soft errors. Soft errors can be coped with a combination of an Error Detection & Correction circuit and scrubbing operation. Smaller geometries and lower voltage of advanced memories makes them more prone to suffer multibit soft errors. A memory structure against multibit soft errors and a suitable scrubbing scheme for it were proposed. This paper introduces a key issue for the scrubbing of the memories with protection against multibit soft errors and the result of the performance analysis from a reliability point of view.