• Journal of the Korea Academia-Industrial cooperation Society
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• v.17 no.3
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• pp.699-707
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• 2016

This paper proposes a low-complexity central processing unit (CPU) that is suitable for deeply embedded systems, including Internet of things (IoT) applications. The core features a 16-bit instruction set architecture (ISA) that leads to high code density, as well as a multicycle architecture with a counter-based control unit and adder sharing that lead to a small hardware area. A co-processor, instruction cache, AMBA bus, internal SRAM, external memory, on-chip debugger (OCD), and peripheral I/Os are placed around the core to make a system-on-a-chip (SoC) platform. This platform is based on a modified Harvard architecture to facilitate memory access by reducing the number of access clock cycles. The SoC platform and CPU were simulated and verified at the C and the assembly levels, and FPGA prototyping with integrated logic analysis was carried out. The CPU was synthesized at the ASIC front-end gate netlist level using a $0.18{\mu}m$ digital CMOS technology with 1.8V supply, resulting in a gate count of merely 7700 at a 50MHz clock speed. The SoC platform was embedded in an FPGA on a miniature board and applied to deeply embedded IoT applications.

• Journal of the Korean Ceramic Society
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• v.47 no.6
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• pp.578-582
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• 2010

$ZrB_2$ has a melting point of $3245^{\circ}C$ and a relatively low density of $6.1\;g/cm^3$, which makes this a candidate for application to ultrahigh temperature environments over $2000^{\circ}C$. Beside these properties, $ZrB_2$ is known to have excellent resistance to thermal shock and oxidation compared with other non-oxide engineering ceramics. In order to enhance such oxidation resistance, SiC was frequently added to $ZrB_2$-based systems. Due to nonsinterability of $ZrB_2$-based ceramics, research on the sintering aids such as $B_4C$ or $MoSi_2$ becomes popular recently. In this study, densification and high-temperature properties of $ZrB_2$-SiC ceramics especially with $B_4C$ are investigated. $ZrB_2$-20 vol% SiC system was selected as a basic composition and $B_4C$ or C was added to this system in some extents. Mixed powders were sintered using hot pressing (HP). With sintered bodies, densification behavior and high-temperature (up to $1400^{\circ}C$) properties such as flexural strength, hardness, and so on were examined.

• Transactions of the Korean Society for Noise and Vibration Engineering
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• v.21 no.11
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• pp.1029-1035
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• 2011

Pressure pulsation of exciting sources that generally occurs on the piping system connected to the discharge of BFP(boiler feed water pump) in power plants causes wave reflection, wave interference, resonance, standing wave and so on. But if the operating speed of the pump is changed, the state of the noise and vibration can be done because characteristics of the exciting source are changed. This paper is to investigate the cause of the noise and vibration occurring on the piping system when the operating speed of BFP is down in accordance with lowering of the power generation. It is approached to two points of view ; Firstly, it is examined whether the pulsation source impacts on the shell mode vibration that vibrates radially across the cross-section of the pipe. But it doesn't affect the shell mode as much as the resonance occurs. Secondly, to find the relation between the pulsation source and the acoustic mode of the piping system, analysis for the piping system by indirect BEM(boundary element method) is carried out. Therefore it is investigated that the mechanism of the noise and vibration relates with acoustic mode of the piping system.

• Journal of information and communication convergence engineering
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• v.6 no.2
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• pp.122-128
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• 2008

Multiprocessor architectures and platforms, such as, a multiprocessor system on chip (MPSoC) recently introduced to extend the applicability of the Moore's law, depend upon concurrency and synchronization in both software and hardware to enhance design productivity and system performance. With the rapidly approaching billion transistors era, some of the main problem in deep sub-micron technologies characterized by gate lengths in the range of 60-90 nm will arise from non scalable wire delays, errors in signal integrity and non-synchronized communication. These problems may be addressed by the use of Network on Chip (NOC) architecture for future System-on-Chip (SoC). We have modeled a concurrent architecture for a customizable and scalable NOC in a system level modeling environment using MLDesigner (from MLD Inc.). Varying network loads under various traffic scenarios were applied to obtain realistic performance metrics. We provide the simulation results for latency as a function of the buffer size. We have abstracted the area results for NOC components from its FPGA implementation. Modeled NOC architecture supports three different levels of quality-of-service (QoS).

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.27 no.10
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• pp.935-940
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• 2016

Directed energy weapon enables to radiate the concentrated energy so as to result in distraction and overload of the target electronics. Analysis on effectiveness of weapon system can be important consideration in order to determine performance and design weapon system. In this paper, air defense weapon system, which is one of directed energy weapon system is studied. In order to analyze the effectiveness, the reflector antenna with high power circularly polarized horn antenna is designed, and power density in axial effective area is simulated and calculated using Friis formula. Through the study, the validity of antenna system is verified, and the effectiveness of directed energy weapon system on the target is evaluated.

• Journal of Bio-Environment Control
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• v.6 no.3
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• pp.216-224
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• 1997

In the recent 10 years the protected cultivation area in Korea has been increased rapidly, and now it is very important issue to develop the heating and cooling system using the renewable energy, because the greenhouse heating and cooling cost is increased with the fossil fuel price rises. Actually the development of the cooling system is more difficult than that of the heating system, since the cooling load of greenhouse in the summer season is 2―3 times larger than the heating load in the winter season. In this study low temperature phase change materials (LTPCM) for the cold storage system were selected and developed. The theoretical and experimental analysis of thermal characteristics of LTPCM makes it possible to control the phase change temperature and stabilize the thermo-physical properties. LTPCM developed in this study has good advantages to be used as the cold storage not only for the house and working space in factory but also for the cold storage of agricultural and live-stock products.

• Journal of Advanced Navigation Technology
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• v.14 no.5
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• pp.684-690
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• 2010

Recently, the NG(Next Generation) system is studied for supporting convergence of various services and multi mode of single terminal. And a demand of user for taking the various services is getting increased, for supporting these services, many systems being able to transmit a large message have been appeared. In the NG system, it has to be supporting the CDMA and WCDMA besides the tele communication systems using OFDM method with single terminal An intergrated system can be improved with adopting of SoC technique. For adopting SoC technique on the intergrated terminal, we have to solve the non linear problem of HPA(High Power Amplifier). Nonlinear characteristic of HPA distorts both amplitude and phase of transmit signal, this distortion cause deep adjacent channel interference. We adopt a polynomial pre-distortion technique for this problem. In this paper, a noble modem design for NG mobile communication service and a method using polynomial pre-distorter with PAPR technique for counterbalancing nonlinear characteristic of the HPA are proposed.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.6 s.348
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• pp.9-17
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• 2006

We proposed a new High-speed CMOS Level Up/Down Shifter circuits that can be used with Dynamic Voltage and Frequency Scaling(DVFS) algorithm, for low power system in the SoC(System-on-Chip). This circuit used to interface between the other voltage levels in each CMOS circuit boundary, or between multiple core voltage levels in a system bus. Proposed circuit have advantage that decrease speed attenuation and duty ratio distortion problems for interface. The level up/down shifter of the proposed circuit designed that operated from multi core voltages$(0.6\sim1.6V)$ to used voltage level for each IP at the 500MHz input frequency The proposed circuit supports level up shifting from the input voltage levels, that are standard I/O voltages 1.8V, 2.5V, 3.3V, to multiple core voltage levels in between of $0.6V\sim1.6V$, that are used internally in the system. And level down shifter reverse operated at 1Ghz input frequency for same condition. Simulations results are shown to verify the proposed function by Hspice simulation, with $0.6V\sim1.6V$ CMOS Process, $0.13{\mu}m$ IBM CMOS Process and $0.65{\mu}m$ CMOS model parameters. Moreover, it is researched delay time, power dissipation and duty ration distortion of the output voltage witch is proportional to the operating frequency for the proposed circuit.

• Proceedings of the KSME Conference
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• 2000.04b
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• pp.531-534
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• 2000

The objective of this investigation is to find effects of the pulsatile flow on the morphological changes of the endothelial cell(E.C.) in blood vessel. The shear flow experiment system is used to get the morphological changes of the E.C. The shapes of E.C. are simulated by the cosine curves and computer simulation is used to calculate the pressure and shear stress fields on the E.C. The inlet boundary condition is given from the measured velocity data of femoral artery. The endothelial cells reduce their heights in the flow field so as to reduce the pressure and wall shear stress on the surface. As the exposed time increases, the shear stress and pressure on the E.C. are reduced under the pulsatile flow. The shear stresses on the cell surface show the minimum values during the deceleration phase.

• The Transactions of the Korea Information Processing Society
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• v.4 no.8
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• pp.1940-1947
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• 1997

The paper describes the design and implementation of Auto-Presentation Feature, Hanuri/C, as Client/Server tool. Hanuri/C provides editing functions for the sequence, period, type, and repeating number of auto-presentation. With the pre-fixed sequences users can get automated presentations through Hanuri/C. The proposed auto-presentation function provides an ability to automatically present the data in the database system without user intervention.