• Title/Summary/Keyword: SoC System

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Phase transformer method and its application (위상변성방식과 그 응용)

  • 오상세
    • 전기의세계
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    • v.13 no.2
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    • pp.1-4
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    • 1964
  • Phase transformation is used to change some phase from phase in A.C. system. We have been used Scott or Fork connection in phase transformation the otherwise phase transformation was constructed from M-G set. From this M-G set, we could make phase shift facilities by mannual. Now, I can derive more easy phase transformation from taking another method. I believe this new phase transformation method in the first thing in the world. And so, I am going to explain about phase transformer construction process. The first, we could devide into equal part of core around the iron core as to be same size. The second, you will make primary and secondary winding on the core. The third, when you will supplied three phase A.C. at the terminal of primary winding you can get e.m.f. inducing of some phase at secondary. And so, we could make phase change from some phase A.C. We can apply this principle in many fields, i.e., freequency changer, phase leader of no use condenser, voltage regulator in keeping balance, and D.C. generator. And more, I will introduce in details concerning main pinciple and theory through following chapter.

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단일칩시스템 설계검증을 위한 가상프로토타이핑

  • Gi, An Do
    • The Magazine of the IEIE
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    • v.30 no.9
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    • pp.59-59
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    • 2003
  • 여러기능들이 복합적으로 통합되고 있는 단일칩시스템을 설계하는데 있어 소프트웨어와 하드웨어를 가능한 일찍 통합하여 검증하는 것이 무엇보다 중요하다. 이러한 조기 통합검증에 필요한 것이 가상프로토타입(Virtual-Prototype) 이다. 본 고에서는 IP(Intellectual Property) 와 단일칩시스템(SoC : System-on-a-Chip) 설계 및 검증에서 가상프로토타입의 필요성과 역할 그리고 이에 관련된 기술들에 대해 정리하고, 프로세싱 코어가 있는 단일칩시스템을 SystemC로 가상프로토타이핑한 사례를 통해 그 유용성을 설명한다.

단일칩시스템 설계검증을 위한 가상프로토타이핑

  • 기안도
    • The Magazine of the IEIE
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    • v.30 no.9
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    • pp.965-975
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    • 2003
  • 여러기능들이 복합적으로 통합되고 있는 단일칩시스템을 설계하는데 있어 소프트웨어와 하드웨어를 가능한 일찍 통합하여 검증하는 것이 무엇보다 중요하다. 이러한 조기 통합검증에 필요한 것이 가상프로토타입(Virtual-Prototype) 이다. 본 고에서는 IP(Intellectual Property) 와 단일칩시스템(SoC : System-on-a-Chip) 설계 및 검증에서 가상프로토타입의 필요성과 역할 그리고 이에 관련된 기술들에 대해 정리하고, 프로세싱 코어가 있는 단일칩시스템을 SystemC로 가상프로토타이핑한 사례를 통해 그 유용성을 설명한다.

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Surveillance System For Underground Power Transmission Lines (초고압 지중선로 감시시스템 연구)

  • Hahn, K.M.;Lee, K.C.;Kim, C.S.
    • Proceedings of the KIEE Conference
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    • 1993.07b
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    • pp.618-620
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    • 1993
  • This system using optical fiber provides various information about underground tunnel and power transmission lines-atmospheric temperature, humidity, oil pressure, flammable gas, cable behavior, and so on. To transmit various data and to keep reliability, optical MUXs are adopted. User can easily operate monitoring software by using GUI.

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The Speed Control System of an Induction Type A.C Servomotor by Vector Control (벡터제어법에 의한 유도형교류 서보전동기의 속도제어에 관한 연구)

  • 홍순일;조철제
    • The Transactions of the Korean Institute of Electrical Engineers
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    • v.38 no.12
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    • pp.1041-1047
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    • 1989
  • In recent years, a.c servomotors have been gradually replacing d.c servomotors in various high-performance applications such as machine tools and industrial robots. Inparticular, the high performance slip-frequency control of an induction motor, which is often called the vector control, is considered ane of th ebest a.c drives. In this paper, the transient state equations and vector control algorithms of an induction type servomotor are described mathematically by using the two- axis theory (d-q coordinates). According to the result of these algorithms, we scheme the speed control system for the motor in which the vector control is adopted to give high performance. Motor drive through a PWM inverter with power MOSFET is controlled so that the actual input current to the motor may track the current reference obtained from a micro-computer (8086 CPU). Driving experiments are performed in the range of 0 to 3000 rpm, and it is verified that high speed response is obtained for this system.

심전계(ECG)의 제작설계

  • 서병설
    • Journal of Biomedical Engineering Research
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    • v.9 no.2
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    • pp.247-250
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    • 1988
  • Laboratory information system (LIS) is a key tool to manage laboratory data in clinical pathology. Our department has developed an information system for routine hematology using down-sized computer system. We have used an IBM 486 compatible PC with 16MB main memory, 210 MB hard disk drive, 9 RS-232C port and 24 pin dot printer. The operating system and database management system were SCO UNIX and SCO foxbase, respectively. For program development, we used Xbase language provided by SCO foxbase. The C language was used for interface purpose. To make the system use friendly, pull-down menu was used. The system connected to our hospital information system via application program interface (API), so the information related to patient and request details is automatically transmitted to our computer. Our system interfaced with fwd complete blood count analyzers(Sysmex NE-8000 and Coulter STKS) for unidirectional data tansmission from analyzer to computer. The authors suggests that this system based on down-sized computer could provide a progressive approach to total LIS based on local area network, and the implemented system could serve as a model for other hospital's LIS for routine hematology.

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A Study on Hetero Junction using NiCuZn Ferrite System for SoP (NiCuZn 페라이트계를 이용한 SoP의 이종접합에 관한연구)

  • Kim, Nam-Hyeon;Kim, Gyeong-Nam
    • Proceedings of the Korean Institute of Surface Engineering Conference
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    • 2012.05a
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    • pp.256-256
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    • 2012
  • SoP용 재료에 응용하기 위하여 NiCuZn 페라이트계 이용한 이종접합의 관한연구를 하였다. NiCuZn 페라이트계와 유전체의 이종접합특성은 XRD, Dilatometer, LCR meter, FE-SEM, EDS 이용하여 물리 화학적 특성을 조사하였다. NiCuZn 페라이트계는 일반적인 세라믹 제조공정을 이용하여 분말을 제조하였으며, 이종접합은 모든 시편에서 잘 진행되었으며 일부 유전체의 이온들이 페라이트 쪽으로 확산이 진행되었으며 NCZF700계는 $900^{\circ}C$ 소결 시편에서 확산이 진행되지 않은 현상이 나타났다.

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System based on Java Card Using XML Digital Signature on Wireless Internet (무선 환경에서 XML 전자서명을 이용한 Java Card 기반 시스템)

  • Jang Chang-Bok;Choi Eui-In
    • The KIPS Transactions:PartC
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    • v.12C no.1 s.97
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    • pp.37-44
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    • 2005
  • As wireless network was developed and Capability of Wireless Phone was increased, M-Commerce was activates In Wireless network environment. User Authentication and Security in E-Commerce Environment is very important, so Authentication Technology, such as WPKI and Hermes System, XML Digital Signature in Wire Network is studying. But if authentication systems was implemented heterogeneous, WPKI is difficult to implement the system, it's not interoperate with authentication system on wire internet, not support XML digital Signature. Hermes system also not interoperate with XML digital signature system. So our paper designed System that can interoperate among digital signature systems and XML document to apply XML digital signature technology on wire network to wireless network, and then implemented system that can XML digital signature to use Java Card.

A Single Transistor-Level Direct-Conversion Mixer for Low-Voltage Low-Power Multi-band Radios

  • Choi, Byoung-Gun;Hyun, Seok-Bong;Tak, Geum-Young;Lee, Hee-Tae;Park, Seong-Su;Park, Chul-Soon
    • ETRI Journal
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    • v.27 no.5
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    • pp.579-584
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    • 2005
  • A CMOS direct-conversion mixer with a single transistor-level topology is proposed in this paper. Since the single transistor-level topology needs smaller supply voltage than the conventional Gilbert-cell topology, the proposed mixer structure is suitable for a low power and highly integrated RF system-on-a-chip (SoC). The proposed direct-conversion mixer is designed for the multi-band ultra-wideband (UWB) system covering from 3 to 7 GHz. The conversion gain and input P1dB of the mixer are about 3 dB and -10 dBm, respectively, with multi-band RF signals. The mixer consumes 4.3 mA under a 1.8 V supply voltage.

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Low Power Test for SoC(System-On-Chip)

  • Jung, Jun-Mo
    • Journal of information and communication convergence engineering
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    • v.9 no.6
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    • pp.729-732
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    • 2011
  • Power consumption during testing System-On-Chip (SOC) is becoming increasingly important as the IP core increases in SOC. We present a new algorithm to reduce the scan-in power using the modified scan latch reordering and clock gating. We apply scan latch reordering technique for minimizing the hamming distance in scan vectors. Also, during scan latch reordering, the don't care inputs in scan vectors are assigned for low power. Also, we apply the clock gated scan cells. Experimental results for ISCAS 89 benchmark circuits show that reduced low power scan testing can be achieved in all cases.