• Journal of Korean Society of Environmental Engineers
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• v.32 no.2
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• pp.201-208
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• 2010

The $SO_2$ and $NO_x$ removal with an activated coke catalyst was conducted by a two-stage reaction which first $SO_2$ was oxidized to $H_2SO_4$ and then $NO_x$ was reduced to $N_2$. But if unreacted sulfur dioxide entered in the second stage, the $NO_x$ reduction was hindered by the reaction with ammonia. In this study, experimental investigations by using lab-scale column apparatus on the product and the reactivity of $SO_2$ with ammonia over coke catalyst which was activated with sulfuric acid was carried out through ultimate analysis DTA, TGA and SEM of catalyst before and after the reaction. Also, the effect of reaction emperature on the reactivity of $SO_2$ with ammonia was determined by means of breakthrough curves with time. The obtained results from this study were summarized as following; Activated cokes were decreased carbon component and increased oxygen and sulfur components in comparison with original cokes. The products over coke catalyst were faced fine crystal of $(NH_4)_2SO_4$, which results in the pressure loss of reacting system. The order of general reactivity in terms of the reaction temperature after breakthrough for $SO_2$ was found to be $150^{\circ}C$ > $200^{\circ}C$ > $100^{\circ}C$. This was related to adsorption amounts of ammonia on the activated cokes.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.4
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• pp.105-116
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• 2008

Today's System-on-a-Chip (SoC) is designed with reusable IP cores to meet short time-to-market requirements. However, the increasing cost of testing becomes a big burden in manufacturing a highly integrated SoC. In this paper, we propose an efficient test access mechanism that exploits an on/off-chip bus bridge for the Advanced High-performance Bus (AHB) and Peripheral Component Interconnect (PCI) bus. The test application time is considerably reduced by providing dedicated test stimuli input paths and response output paths, and by excluding the bus direction tumaround delays. Experimental results show that area overhead and testing times are considerably reduced in both functional and structural test modes. The proposed technique can be a lied to the other types of on/off-chip bus bridges.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.1
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• pp.69-78
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• 2010

To implement the high performance SoC, we propose the flying master bus architecture that a specially defined master named as the flying master directly accesses the selected slaves with no regard to the bus protocol. The proposed bus architecture was implemented through Verilog and mapped the design into Hynix 0.18um technology. As master and slave wrappers have around 150 logic gate counts, the area overhead is still small considering the typical area of modules in SoC designs. In TLM performance simulation about proposed architecture, 25~40% of transaction cycle and 43~60% of bus efficiency are increased and 43~77% of request cycle is decreased, compared with conventional bus architecture. Conclusively, we assume that the proposed flying master bus architecture is promising as the leading candidate of the bus architecture in the aspect of performance and efficiency.

• Journal of Hydrogen and New Energy
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• v.20 no.1
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• pp.38-44
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• 2009

Recently, the research focused on fuel cell hybrid vehicles (FCHVs) is becoming an attractive solution due to environmental pollution generated by fossil fuel vehicles. The proper energy control strategy will result in extending the fuel cell lifetime, increasing of energy efficiency and an improvement of vehicle performance. Battery state of charge (SoC) is an important quantity and the estimation of the SoC is also the basis of the energy control strategy for hybrid electric vehicles. Estimating the battery's SoC is complicated by the fact that the SoC depends on many factors such as temperature, battery capacitance and internal resistance. In this paper, battery charging time estimated by SoC is studied by using the speed response and current response. Hybrid system is consist of a fuel cell unit and a battery in series connection. For experiment, speed response of vehicle and current response of battery were determined under different state of charge. As the results, the optimal battery charging time can be estimated. Current response time was faster than RPM response time at low speed and vice versa at high speed.

• Journal of Power Electronics
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• v.15 no.4
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• pp.1105-1118
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• 2015

Battery energy storage devices (ESDs) have become more and more commonplace to maintain the stability of islanded power systems. Considering the limitation in inverter capacity and the requirement of flexibility in the ESD, the droop control was implemented in paralleled ESDs for higher capacity and autonomous operation. Under the conventional droop control, state-of-charge (SoC) errors between paralleled ESDs is inevitable in the discharging operation. Thus, some ESDs cease operation earlier than expected. This paper proposes an adaptive accelerating parameter to improve the performance of the SoC error eliminating droop controller under the constraints of a microgrid. The SoC of a battery ESD is employed in the active power droop coefficient, which could eliminate the SoC error during the discharging process. In addition, to expedite the process of SoC error elimination, an adaptive accelerating parameter is dedicated to weaken the adverse effect of the constraints due to the requirement of the system running. Moreover, the stability and feasibility of the proposed control strategy are confirmed by small-signal analysis. The effectiveness of the control scheme is validated by simulation and experiment results.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.1209-1212
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• 2003

In this paper, we propose a SDRAM Controller. The SDRAM is often used a mainstream memory as embedded system memory due to its short latency, burst access and pipeline features. The proposed Controller provides essential functions for SDRAM initialization, read/write accesses, memory refresh and Burst access. Furthermore, the proposed controller is implemented in the form of SOFT IP. Therefore, it reduces the designer's effort greatly.

• Proceedings of the Korean Information Science Society Conference
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• 2004.04a
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• pp.943-945
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• 2004

임베디드 소프트웨어는 타겟 시스템의 자원과 타이밍에 민감하므로 실제 타겟 시스템과 동일한 환경에서 디버깅해야한다. 이를 위한 기존의 기법들은 타겟 시스템의 자원에 직접적으로 접근하여 시스템 상태를 조사하거나 제어한다. 그러나 이러한 기법들은 내부 신호나 자원에 대한 접근이 제한되어 있는 SoC (System-On-a-Chip) 프로그램을 디버깅하기는 부적합하다. 본 논문에서는 산업 표준화된 JTAG을 기반으로 공개 소프트웨어인 gob를 연동하여 SoC 소프트웨어를 디버깅하는 도구를 제안한다. 따라서 본 도구는 타겟 시스템에 영향을 주지 않고 경제적으로 디버깅할 수 있는 환경을 제공한다.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.665-666
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• 2006

By adding user interface to the usual router, an improved functional router is implemented In this paper, we design the DWT(Discrete Wavelet Transform) for JPEG2000 CODEC. The DWT is developed based on ARM-based Excalibur, and the system contains DMA processor, Slave interface, DWT filter, Controller. The architecture of the prposed DWT is verified using Altera QuartusII.

• Korean Security Journal
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• no.4
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• pp.319-341
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• 2001

Most of protecting security activity is carried out by manpower partly by security equipment. The protecting security market and the area of protecting security activity is increasing in spite of change of economic and social environment situation. For more effective protecting security activity, the coordination of electronic equipment and manpower is required. So some application method is suggested throughout the thesis, which is especially focused on new approaching method. The integration of intrusion detecting system, C.C.TV system and Access control system is introduced for general application in chapter III, and some application systems are proposed for protecting security activity in chapter IV. But the security equipment is only aid for manpower, so manpower and equipment should be coordinated well.

• Proceedings of the KIEE Conference
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• 1996.07a
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• pp.606-608
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• 1996

In this paper, a new control scheme based on deadbeat control with disturbance observer for voltage controlled Inverter system is proposed. The inverter system is modelled as the 4th-order system treating R load current variation caused by disturbance. So the disturbance observer exists in the state observer. By using the pole placement strategy, the observer estimates the state and disturbance variable of the next sampling instant. Simulation results so show that The proposed scheme has robust feature against disturbance.