• Title/Summary/Keyword: SoC System

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Simulation-Based Fault Analysis for Resilient System-On-Chip Design

  • Han, Chang Yeop;Jeong, Yeong Seob;Lee, Seung Eun
    • Journal of information and communication convergence engineering
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    • v.19 no.3
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    • pp.175-179
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    • 2021
  • Enhancing the reliability of the system is important for recent system-on-chip (SoC) designs. This importance has led to studies on fault diagnosis and tolerance. Fault-injection (FI) techniques are widely used to measure the fault-tolerance capabilities of resilient systems. FI techniques suffer from limitations in relation to environmental conditions and system features. Moreover, a hardware-based FI can cause permanent damage to the target system, because the actual circuit cannot be restored. Accordingly, we propose a simulation-based FI framework based on the Verilog Procedural Interface for measuring the failure rates of SoCs caused by soft errors. We execute five benchmark programs using an ARM Cortex M0 processor and inject soft errors using the proposed framework. The experiment has a 95% confidence level with a ±2.53% error, and confirms the reliability and feasibility of using proposed framework for fault analysis in SoCs.

A Case Study of Implementation of Concurrent Drug Utilization Review System at a General Hospital (동시적 의약품 사용평가(cDUR) 시스템 구축 및 적용 사례 연구 : 국내 한 대학병원을 중심으로)

  • Choi, Jong Soo;Kim, Dongsoo
    • Journal of Korean Institute of Industrial Engineers
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    • v.39 no.1
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    • pp.20-29
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    • 2013
  • Medical errors such as adverse drug event, improper transfusion, wrong-site surgery, mistaken patient identity and so on commonly occur at health care practice. Information technology, like Drug Utilization Review(DUR) system which reviews, analyzes, and interprets medication data when prescribing, can play a key role in reducing such medical errors and improving patient safety. Korean Government has guided all hospitals to implement concurrent DUR(cDUR) system, which is the first case worldwide in that all healthcare providers have to use cDUR system when prescribing. This paper introduced a case study that a tertiary hospital has integrated the cDUR system into its comprehensive Hospital Information System(HIS) and analyzed the whole prescription data during a week right after adoption of cDUR system. Considering technical strength and weakness, the cDUR system was integrated into the HIS, using Broker Servers for minimizing doctors' anxiety. As the quantitative analysis of the whole prescription data, DUR conflict events, which mainly included duplicate medications and contra-indicated drug interactions for outpatients, were 2.77%. Although only 0.7% is for the contra-indicated drug interactions, it will be greatly devoted to achieve the purpose of DUR such as improving patient safety.

Low Power Level-Up/Down Shifter with Single Supply for the SoC with Multiple Supply (다중전원 SoC용 저전력 단일전원 Level-Up/Down Shifter)

  • Woo, Young-Mi;Kim, Doo-Hwan;Cho, Kyoung-Rok
    • The Journal of the Korea Contents Association
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    • v.8 no.3
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    • pp.25-31
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    • 2008
  • We propose a low power level-up/down shifter with single supply that can be used at SoC with multiple supply. The proposed circuit interfaces IPs which are operated on the different supply voltages. The circuit is designed with a single supply that decreases the low power consumption and the complexity of supply routing and layout. The proposed circuit operated at 500MHz for level-up and at 1GHz for level-down. The level-up/down shifter improves noise immunity of the system at I/O circuit. The circuit is evaluated for 1.8V, 2.5V, 3.3V supply with 0.18um CMOS technology, respectively.

Correlation Analysis between BLE-based RSSI and SoC Internal or Local Temperature (BLE 기반 RSSI와 SoC 내부 또는 국부 온도의 상관관계)

  • Kim, Seong-Chang;Lee, Min-Jeong;Oh, Sung-Bhin;Kim, Jun-Su;Kim, Jin-Ho
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2022.05a
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    • pp.89-91
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    • 2022
  • Wireless sensor networks(WSN), which are mainly used for indoor positioning, rely on the accuracy of RSSI. This RSSI is sensitive to several factors that cause interference, and there are foreign studies showing that temperature has a large effect on RSSI in indoor/outdoor environment among several factors. The temperature of the indoor space is uneven due to heat sources or air cooling systems indoors, and temperature changes frequently occur at certain locations. In particular, in case of an indoor fire, the accurate positioning system is required to guide an evacuation route, but a high temperature is locally formed due to a fire around the receiver, so the RSSI value could be influenced. In this paper, the effect on RSSI is studied by analyzing the correlation between SoC internal/local temperature and RSSI.

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Fabrication of Bi-2212/$SrSO_4$ Composite Superconductors by Melting Powder Mixtures

  • Kim, Kyu-Tae;Jang, Seok-Hern;Lim, Jun-Hyung;Park, Eui-Cheol;Joo, Jin-Ho;Lee, Hoo-Jeong;Hong, Gye-Won;Kim, Chan-Joong;Kim, Hye-Rim;Hyun, Ok-Bae
    • Proceedings of the Korean Powder Metallurgy Institute Conference
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    • 2006.09b
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    • pp.1245-1246
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    • 2006
  • We fabricated Bi-2212/$SrSO_4$ composite superconductors and evaluated the effects of the powder mixing method and melting temperature on their microstructure and superconducting properties. The Bi-2212 powders were mixed with $SrSO_4$ by hand-mixing (HM) and planetary ball milling (PBM) and then the powder mixtures were melted at $1100^{\circ}C{\sim}1200^{\circ}C$, solidified, and annealed. We found that the powder mixture prepared by PBM was finer and more homogeneously mixed than that prepared by HM, resulting in more homogeneous microstructure and smaller $SrSO_4$ and second phases after annealing.

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Implementation of JPEG Encoder and Decoder with SystemC (SystemC를 이용한 JPEG 인코더/디코더의 구현)

  • You, Myoung-Keun;Song, Gi-Yong
    • Proceedings of the Korea Institute of Convergence Signal Processing
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    • 2006.06a
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    • pp.89-92
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    • 2006
  • 본 논문에서는 SystemC를 이용하여 데이터를 압축하는 JPEG의 인코더와 디코더 구현에 대하여 기술한다. SystemC는 SoC의 설계생산성을 높이기 위해 high-level abstraction에 기반하여 시스템을 모델링하고 명시하는 시스템 수준 설계 언어이고, JPEG은 DCT와 Huffman 코드를 이용하여 정지영상 정보를 압축하는 알고리즘이다. 설계된 JPEG 인코더와 디코더 모듈의 동작을 검증하기 위하여 인코더 모듈에 $16{\times}16$ 크기의 픽셀 RGB 데이터를 입력하고, 디코더 모듈에 인코더 모듈의 출력을 입력으로 연결하여 최종 출력되는 데이터를 비교 및 분석하여 확인하였다.

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Reconfigurable SoC Design with Hierarchical FSM and Synchronous Dataflow Model (Hierarchical FSM과 Synchronous Dataflow Model을 이용한 재구성 가능한 SoC의 설계)

  • 이성현;유승주;최기영
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.40 no.8
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    • pp.619-630
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    • 2003
  • We present a method of runtime configuration scheduling in reconfigurable SoC design. As a model of computation, we use a popular formal model of computation, hierarchical FSM (HFSM) with synchronous dataflow (SDF) model, in short, HFSM-SDF model. In reconfigurable SoC design with HFSM-SDF model, the problem of configuration scheduling becomes challenging due to the dynamic behavior of the system such as concurrent execution of state transitions (by AND relation), complex control flow (HFSM), and complex schedules of SDF actor firing. This makes it hard to hide configuration latency efficiently with compile-time static configuration scheduling. To resolve the problem, it is necessary to know the exact order of required configurations during runtime and to perform runtime configuration scheduling. To obtain the exact order of configurations, we exploit the inherent property of HFSM-SDF that the execution order of SDF actors can be determined before executing the state transition of top FSM. After obtaining the order information and storing it in the ready configuration queue (ready CQ), we execute the state transition. During the execution, whenever there is FPGA resource available, a new configuration is selected from the ready CQ and fetched by the runtime configuration scheduler. We applied the method to an MPEG4 decoder and IS95 design and obtained up to 21.8% improvement in system runtime with a negligible overhead of memory usage.

Forming Conditions of Curved Glass using Force Applying System of Glass Molding System (유리성형시스템의 힘측정기반 가압장치를 이용한 곡면유리 성형조건)

  • Hong, Tae Kyeong;Kim, Gab Soon
    • Journal of the Korean Society for Precision Engineering
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    • v.31 no.4
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    • pp.335-342
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    • 2014
  • This paper describes the forming conditions of smart-phone curved glass using the glass molding system with force applying system. The force applying system is composed of a body, a motor and gear, a rectilinear movement structure, a force sensor, a LVDT sensor (Linear Variable Differential Transformer), a up and down moving block, and so on. The glass molding system for characteristic test to find the forming conditions consists of the force applying system and a chamber, a metallic mold, a upper heater, a lower heater and so on. The characteristic test for forming conditions of smart-phone curved glass was carried out at forming temperature $620^{\circ}C$ and $650^{\circ}C$ using the glass molding system. As a result of the characteristic test, the forming conditions of curved glass could be found, and it is thought that the conditions can be used to apply to the system for producing in large quantities.

Measuring ultrasonic TOF using Zynq baremetal Multiprocessing (Zynq 기반 baremetal 멀티프로세싱에 의한 초음파 TOF 측정)

  • Kang, Moon ho
    • Journal of the Institute of Electronics and Information Engineers
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    • v.54 no.6
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    • pp.93-99
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    • 2017
  • In this research the TOF (time of flight) of ultrasonic signal is measured using Xilinx's Zynq SoC (system on chip). The TOF is calculated from the difference between periods during which RF (radio frequency) and ultrasonic signals come across a distance, and then travelling distance is obtained by multiplying the TOF by the ultrasonic speed in the air. For this purpose, a ultrasonic pulse is generated from a Zynq's internal ADC, a FIR (finite impulse response) filter, and a Kalman filter. And a RF reference pulse is generated from a RF interface. Based on baremetal multiprocessing, the Kalman filter and the RF interface are c-programmed on Zynq's dual processor cores, with other components fabricated on Zynq's FPGA. With this HW/SW co-design, both lower resource utilization and much smaller designing period were obtained than the HW design. As a design tool, Vivado IDE(integrated design environment) is used to design the whole signal processing system in hierarchical block diagrams.

Selective chemical vapor deposition of $\beta$-SiC on Si substrate using hexamethyldisilane/HCl/$H_{2}$ gas system (Hexamethyldisilane/HCl/$H_{2}$ gas system을 이용한 Si 기판에서 $\beta$-SiC의 선택적 화학기상증착)

  • 양원재;김성진;정용선;오근호
    • Journal of the Korean Crystal Growth and Crystal Technology
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    • v.9 no.1
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    • pp.14-19
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    • 1999
  • Using a single precursor of hexamethyldisilane $(Si_{2}(CH_{3})_{6})$, $\beta$-SiC film was successfully deposited on a Si substrate at $1100^{\circ}C$ by a chemical vapor deposition method. Selectivity of SiC deposition on a Si substrate partially covered with a masking material was investigated by introducing HCl gas into hexamethyldisilane/$H_{2}$ gas system during the deposition. The schedule of the precursor and HCl gas flows was modified so that the selectivity of SiC deposition between a Si substrate and a mask material should be improved. It was confirmed that the selectivity of SiC deposition was improved by introducing HCl gas. Also, the pulse gas flow technique was effective to enhance the selectivity.

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