• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.1
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• pp.52-60
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• 2003

For a System-on-a-Chip(SoC) comprised of multiple IP cores, various design techniques have been proposed to provide diverse test link configurations. In this paper, we introduce a new flag based Wrapped Core Linking Module (WCLM) that enables systematic integration of IEEE 1149.1 TAP'd cores and P1500 wrapped cores with requiring least amount of area overhead compared with other state-of-art techniques. The design preserves compatibility with standards and scalability for hierarchical access.

• Annual Conference of KIPS
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• 2008.11a
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• pp.810-813
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• 2008

본 논문에서 연구하고 구현된 JTAG(Joint Test Action Group) Writer는 하나의 SoC(System On a Chip)만 지원하도록 설계된 기존 제품의 단점을 보완할 수 있도록 각 SoC의 제조 회사에서 제공하는 BSDL(Boundary Scan Description Language)을 이용하여 여러 가지 SoC에 쉽게 사용할 수 있도록 모듈화 했다. 그리고 기존 제품들이 사용하고 있는 직렬 포트나 병렬 포트 대신 안정적이고 편리한 USB(Universal Serial Bus) 접속규격을 지원하도록 개선했다.

• Progress in Superconductivity
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• v.8 no.1
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• pp.108-112
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• 2006

We fabricated Bi-2212/$SrSO_4$ bulk superconductors by the casting process and evaluated the effects of the powder mixing method and annealing temperature on the texture, microstructure, and critical current. In the process, the Bi-2212 powders were mixed with $SrSO_4$ by hand-mixing(HM) and planetary ball milling(PBM) method and then the powder mixtures were melted at $1100^{\circ}C{\sim}1200^{\circ}C$, solidified, and annealed. We observed that the rod made by the PBM had a more homogeneous microstructure and smaller $SrSO_4$ and second phases than that of the rod made by the HM, resulting in increased $I_c$. The $I_c$ of the rod also depended on the annealing temperature and the highest $I_c$ was obtained to be 200 A when prepared by HM at $1200^{\circ}C$ and annealed at $810^{\circ}C$ which is probably due to the moderate density and 2212 texture and the smaller and less second phase compared to that at higher temperature. The possible causes of the variations of $I_c$ with the powder mixing method and annealing temperature were related to the microstructural evolution based on the SEM, EPMA, and DTA analyses.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2010.11a
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• pp.467-468
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• 2010

• The Journal of the Korea Contents Association
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• v.9 no.3
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• pp.9-19
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• 2009

In this paper, we propose a novel hardware architecture to facilitate the applicable SoC chip design of H.264/SVC which has a great deal of advancement in the international standardization in recent. Moreover, a new C-model simulator based on the proposed hardware system will be presented to support optimal SoC circuit development. Since the proposed SVC decoder is consist of some hardware engine for processing of major decoding tools and core processor for software processing, the system is simply implemented with the conventional embedded system. To improve the feasibility and applicability, and reduce the decoder complexity, the hardware decoder architecture is constructed with only the consideration of IPPP structure scalability without using the full B-picture. Finally, we present results of decoder hardware implementation and decoded picture to show the effectiveness of the proposed hardware architecture and C-model simulator.

• International Journal of Aeronautical and Space Sciences
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• v.18 no.4
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• pp.675-687
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• 2017

In the aerospace industry, we have produced various models according to operational conditions and the environment after development of the base model is completed. Therefore, when design change is necessary, there are modification and updating costs of the circuit whenever environment variables change. For these reasons, recently, in various fields, system designs that can flexibly respond to changing environmental conditions using field programmable gate arrays (FPGAs) are attracting attention, and the rapidly changing aerospace industry also uses FPGAs to organize the system environment. In this paper, we design the controller area network (CAN) intellectual property (IP) protocol used instead of the avionics protocol that includes ARINC-429 and MIL-STD-1553, which are not suitable for small unmanned aerial vehicle (UAV) systems at the register transistor logic (RTL) level, which does not depend on the FPGA vender, and we verify the performance. Consequentially, a Spartan 6 FPGA model-based system on chip (SoC) including an embedded system is constructed by using the designed CAN communications IP and Xilinx Microblaze, and the configured SoC only recorded an average 32% logic element usage rate in the Spartan 6 FPGA model.

• Proceedings of the SAREK Conference
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• 2008.11a
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• pp.75-79
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• 2008

Since tunnel construction order was placed one by one, various sensors and actuators installed at the RTU and higher level system in each tunnel maintenance office had their own protocols depending on construction company. The TGMS testbed established on the extended region of Yong-dong Highway, for example, did not have consistent protocol between each automation levels and management levels without considering the functions and/or roles of each level. The management sever in each tunnel was simply networked to the TGMS server. Therefore, it is impossible to implement a new control algorithm as well as to integrate each other since each tunnel was constructed by different company. So, if the construction company is out of business, there is no way to maintain the corresponding tunnel effectively. In order to solve this problem, all the necessary standard protocols was established between automation level and management levels. These interface standards provide the clear classification between individual tunnel system and tunnel management system. So, even if construction company is different, its effect is minimized, so that it is expected to successfully establish PC based TGMS.

• Journal of the Korean Ceramic Society
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• v.48 no.6
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• pp.584-588
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• 2011

In this work, effects of limestone powder on hydration of $C_3A-CaSO_4{\cdot}2H_2O$ system was discussed based on the XRD Quantitative analysis, and the possibility of Delayed Ettringite Formation was also discussed. The early hydration of $C_3A$ was delayed by addition of $CaCO_3$ powder. The delay effect was enhanced by increasing of $CaCO_3$ content and finer powder of $CaCO_3$ addition. After consumption of $CaSO_4{\cdot}2H_2O$, the reaction of $CaCO_3$ is started. Delayed Ettringite Formation would take place because monosulfoaluminate is not stable in presence of $CaCO_3$. In order to prevent the delayed ettringite formation in $C_3A-CaSO_4{\cdot}2H_2O-CaCO_3$ system, the reduction of monosulfoaluminate formation is important. Therefore, by increasing the amount of $CaCO_3$ addition and finer $CaCO_3$ powder addition, the delayed ettringite formation can be prevented.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.13 no.1
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• pp.348-354
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• 2012

This paper presents a framework for quantitative software development performance measurement and analysis based on characteristics of software in System on Chip (SoC) industry, one of the semiconductor businesses. In this paper, we propose a measurement model based on not only theoretical model (Performance Pyramid) but also characteristics of SoC embedded software. Quantitative software development performance measurement is not just collecting indicators but analyzing quality, cost, and delivery (QCD) of collected indicators. Externally, it is possible for programmers to develop software meeting customers' needs. Internally, more efficient software development can be possible through the visible productivity increase. Using the proposed framework, the paper quantitatively measures embedded software development performance.

• Journal of IKEEE
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• v.23 no.2
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• pp.388-394
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• 2019

This paper describes a design of security system-on-chip (SoC) that integrates a Cortex-M0 CPU with an AAW (ARIA-AES- Whirlpool) crypto-core which implements two block cipher algorithms of ARIA and AES and a hash function Whirlpool into an unified hardware architecture. The AAW crypto-core was implemented in a small area through hardware sharing based on algorithmic characteristics of ARIA, AES and Whirlpool, and it supports key sizes of 128-bit and 256-bit. The designed security SoC was implemented on FPGA device and verified by hardware-software co-operation. The AAW crypto-core occupied 5,911 slices, and the AHB_Slave including the AAW crypto-core was implemented with 6,366 slices. The maximum clock frequency of the AHB_Slave was estimated at 36 MHz, the estimated throughputs of the ARIA-128 and the AES-128 was 83 Mbps and 78 Mbps respectively, and the throughput of the Whirlpool hash function of 512-bit block was 156 Mbps.