• Proceedings of the Korean Institute of Communication Sciences Conference
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• 2004.11a
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• pp.258-258
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• 2004

• Journal of Korea Multimedia Society
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• v.17 no.3
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• pp.324-332
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• 2014

This paper presents a programmable System-On-a-chip for various embedded applications that need Neural Network computations. The system is fully implemented into Field-Programmable Gate Array (FPGA) based prototyping platform. The SoC consists of an embedded processor core and a reconfigurable hardware accelerator for neural computations. The performance of the SoC is evaluated using real image processing applications, such as optical character recognition (OCR) system.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.1
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• pp.57-64
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• 2006

Multiprocessor system on chip (MPSoC) platforms has set a new innovative trend for the SoC design. Quality of service parameters and performance matrix are leading to the adoption of new design methodology for SoC, which will incorporate highly scalable, reusable, predictable, cost and energy efficient platform not only for underlying communication backbone but also for the entire system architecture of NOC. Like the layered architecture for the communication backbone of NOC, we have proposed the entire system architecture for NOC to be a seven layered architecture in itself. Such a platform can separate the domain specific issues which will model concurrency along with the synchronization issues more effectively. For such a layered architecture, model of computation will provide a framework to that can model concurrency and synchronization issues which are natural for any application. Therefore it becomes extremely important to use a right computation model in a specific NOC region.

• Journal of Korea Multimedia Society
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• v.13 no.7
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• pp.1051-1061
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• 2010

Since Korean mobile communication companies each use different mobile platforms, developers must configure and translate their game contents to run under each of the platforms so that they can be serviced correctly. Nevertheless, such translation tasks require lengthy times and costs. This is one of the reasons why a variety of contents could not be provided. In order to mitigate such difficulty, this paper implemented an automatic mobile contents translating system that automatically translates mobile C game contents of the GNEX platform to mobile java contents of the Android platform as a smart platform using a source-level contents translator. The GNEX C-to-Android Java automatic contents translation system helps minimize the amount of time and cost required in servicing contents to different mobile communication companies by promptly translating a platform-specific-content to run under other platforms. Also, the automatic translation and servicing of existing contents increases the reusability of these contents and also the productivity of new contents thereby offering users with a more variety of games.

• Journal of the Korean Institute of Intelligent Systems
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• v.14 no.4
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• pp.512-516
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• 2004

Context-aware computing has been attracting the attention as an approach to alleviating the inconvenience in human-computer interaction. This paper proposes a context-aware system architecture to be implemented on an SoC(System-on-a-Chip). The proposed architecture supports sensor abstraction, notification mechanism for context changes, modular development, easy service composition using if-then rules, and flexible context-aware service implementation. It consists of the communication unit, the processing unit, the blackboard, and the rule-based system unit, where the first three components reside in the microprocessor part of the SoC and the rule-based system unit is implemented in hardware. For the proposed architecture, an SoC system has been designed and tested in an SoC development platform called SystemC and the feasibility of the behavoir modules for the microprocessor part has been evaluated by implementing software modules on the conventional computer platform. This SoC-based context-aware system architecture has been developed to apply to mobile intelligent robots which would assist old people at home in a context-aware manner.

• ETRI Journal
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• v.30 no.1
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• pp.141-151
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• 2008

In this paper, we introduce a new verification platform with ARM- and DSP-based multiprocessor architecture. Its simple communication interface with a crossbar switch architecture is suitable for a heterogeneous multiprocessor platform. The platform is used to verify the function and performance of a DVB-T baseband receiver using hardware and software partitioning techniques with a seamless hardware/software co-verification tool. We present a dual-processor platform with an ARM926 and a Teak DSP, but it cannot satisfy the standard specification of EN 300 744 of DVB-T ETSI. Therefore, we propose a new multiprocessor strategy with an ARM926 and three Teak DSPs synchronized at 166 MHz to satisfy the required specification of DVB-T.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2010.11a
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• pp.467-468
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• 2010

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.2
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• pp.106-114
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• 2010

We proposed an unified design methodology and verification platform for giga-scale System on Chip (SoC). According to the growth of VLSI integration, the existing RTL design methodology has a limitation of a production gap because a design complexity increases. A verification methodology need an evolution to overcome a verification gap. The proposed platform includes a high level synthesis, and we develop a power-aware verification platform for low power design and verification automation using it's results. We developed a verification automation and power-aware verification methodology based on control and data flow graph (CDFG) and an abstract level language and RTL. The verification platform includes self-checking and the coverage driven verification methodology. Especially, the number of the random vector decreases minimum 5.75 times with the constrained random vector algorithm which is developed for the power-aware verification. This platform can verify a low power design with a general logic simulator using a power and power cell modeling method. This unified design and verification platform allow automatically to verify, design and synthesis the giga-scale design from the system level to RTL level in the whole design flow.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.651-654
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• 2005

In this paper, we designed ECC(Elliptic Curve Cryptographic) Processor with Bus-splitting mothod for embedded SoC. ECC SIP is designed by VHDL RTL modeling, and implemented reusably through the procedure of logic synthesis, simulation and FPGA verification. To communicate with ARM9 core and SIP, we designed SIP bus functional model according to AMBA AHB specification. The design of ECC Processor for platform-based SoC is implemented using the design kit which is composed of many devices such as ARM9 RISC core, memory, UART, interrupt controller, FPGA and so on. We performed software design on the ARM9 core for SIP and peripherals control, memory address mapping and so on.

• Journal of Korea Multimedia Society
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• v.13 no.4
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• pp.609-617
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• 2010

Since Korean mobile communication companies each use different mobile platforms, developers must configure and translate their game contents to run under each of the platforms so that they can be serviced correctly. Nevertheless, such translation tasks require lengthy times and costs. This is one of the reasons why a variety of contents could not be provided. In order to mitigate such difficulty, this paper implemented an automatic mobile contents translating system that automatically translates mobile C game contents of the GNEX platform to mobile java contents of the WIPI platform. The GNEX C-to-WIPI Java automatic contents translation system helps minimize the amount of time and cost required in servicing contents to different mobile communication companies by promptly translating a platform-specific-content to run under other platforms. Also, the automatic translation and servicing of existing contents increases the reusability of these contents and also the productivity of new contents thereby offering users with a more variety of games.