• Proceedings of the IEEK Conference
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• 2002.07a
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• pp.164-167
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• 2002

This paper presents the design of Rijndael crypto-processor with 128 bits, 192 bits and 256 bits key size. In October 2000 Rijndael cryptographic algorithm is selected as AES(Advanced Encryption Standard) by NIST(National Institute of Standards and Technology). Rijndael algorithm is strong in any known attacks. And it can be efficiently implemented in both hardware and software. We implement Rijndael algorithm in hardware, because hardware implementation gives more fast encryptioN/decryption speed and more physically secure. We implemented Rijndael algorithm for 128 bits, 192 bits and 256 bits key size with VHDL, synthesized with Synopsys, and simulated with ModelSim. This crypto-processor is implemented using on-the-fly key generation method and using lookup table for S-box/SI-box. And the order of Inverse Shift Row operation and Inverse Substitution operation is exchanged in decryption round operation of Rijndael algorithm. It brings about decrease of the total gate count. Crypto-processor implemented in these methods is applied to mobile systems and smart cards, because it has moderate gate count and high speed.

• IEIE Transactions on Smart Processing and Computing
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• v.4 no.3
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• pp.152-157
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• 2015

Various power supply noise sources in a system integrated circuit degrade the performance of a low dropout (LDO) regulator. In this paper, a capacitor-less low dropout regulator for enhanced power supply rejection is proposed to provide good power supply rejection (PSR) performance. The proposed scheme is implemented by an additional capacitor at a gate node of a pass transistor. Simulation results show that the PSR performance of the proposed LDO regulator depends on the capacitance value at the gate node of the pass transistor, that it can be maximized, and that it outperforms a conventional LDO regulator.

• Proceedings of the Korean Society of Computer Information Conference
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• 2011.06a
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• pp.29-30
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• 2011

본 논문에서는 스마트폰 얼굴인식을 통해 출입을 관리하는 시스템을 설계하고 구현한다. 이를 위해 스마트폰에서 얼굴인식을 위한 사용가능한 다양한 알고리즘을 조사하였다. 얼굴 인식의 첫 단계는 얼굴검출이며 다음 단계는 얼굴인식이다. 얼굴 검출을 위해서는 컬러 세그멘테이션, 템플릿매칭 등의 알고리즘을 적용하였으며, 얼굴 인식을 위해서는 PCA(Principal Component Analysis)에 기반을 둔 Eigenface와 LDA(Linear Discriminant Analysis)에 기반을 둔 Fisherface를 비교하여 구현하고 적용하였다. 스마트 폰의 제한된 하드웨어에서 얼굴인식 시스템을 구현하는 관계로 알고리즘의 정확도와 알고리즘의 계산 복잡도 사이에서 적절한 조절이 필요하였다.

• Journal of Power Electronics
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• v.15 no.3
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• pp.685-694
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• 2015

The power loss of the controllable switches in modular multilevel converter (MMC) HVDC transmission systems is an important factor, which can determine the design of the operating junction temperatures. Due to the dc current component, the approximate calculation tool provided by the manufacturer of the switches cannot be used for the losses of the switches in the MMC. Based on the enabled probabilities of each SM in an arm, the current analytical models of the switches can be determined. The average and RMS currents can be obtained from the corresponding current analytical model. Then, the conduction losses can be calculated, and the switching losses of the switches can be estimated according to the upper limit of the switching frequency. Finally, the thermal resistance model of the switches can be utilized, and the junction temperatures can be estimated. A comparison between the calculation and PSCAD simulation results shows that the proposed method is effective for estimating the junction temperatures of the switches in the MMC.

• Journal of the Korea Society of Computer and Information
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• v.13 no.6
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• pp.195-201
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• 2008

We proposed that is suitable network environment and wire/wireless communication network, easy of implementation, security level preservation, scalable & reconfigurable to TCP/IP protocol architecture to implement suitable smart card MS-Serpent cryptographic algorithm for smart card by hardware base chip level that software base is not implement. Implemented MT-Serpent cryptosystem have 4,032 in gate counter and 406.2Mbps@2.44MHz in throughput. Implemented MS-Serpent cryptographic algorithm strengthens security vulnerability of TCP/IP protocol to do to rescue characteristic of smart card and though several kind of services are available and keep security about many user in wire/wireless environment, there is important purpose.

• Proceedings of the KIEE Conference
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• 2003.07b
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• pp.1270-1272
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• 2003

Smart card system is being used in many countries to improve access to their transportation systems. Especially for subway system that typically see high volumes of passengers at specific times of the days, it's critical to find a ray to collect fares without unnecessarily delaying passengers. The card consists of antenna, modulation and demodulation block, power supply module and memory. The antenna receives the power and data signal from reader. The FRAM is used as the inner memory. And it is a non-volatile memory and complements the problems, that is high consumption and low data processing speed, of using conventional EEPROM in the passive smart cart. In this paper, we analyze and design the RF passive smart card to apply to the fare collection for the subway gate system.

• Nuclear Engineering and Technology
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• v.53 no.10
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• pp.3327-3334
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• 2021

Present electric grids are advanced to integrate smart grids, distributed resources, high-speed sensing and control, and other advanced metering technologies. Cybersecurity is one of the challenges of the smart grid and nuclear plant digital system. It affects the advanced metering infrastructure (AMI), for grid data communication and controls the information in real-time. The research article is emphasized solving the nuclear and smart grid hardware security issues with the integration of field programmable gate array (FPGA), and implementing the latest Time Authenticated Cryptographic Identity Transmission (TACIT) cryptographic algorithm in the chip. The cryptographic-based encryption and decryption approach can be used for a smart grid distribution system embedding with FPGA hardware. The chip design is carried in Xilinx ISE 14.7 and synthesized on Virtex-5 FPGA hardware. The state of the art of work is that the algorithm is implemented on FPGA hardware that provides the scalable design with different key sizes, and its integration enhances the grid hardware security and switching. It has been reported by similar state-of-the-art approaches, that the algorithm was limited in software, not implemented in a hardware chip. The main finding of the research work is that the design predicts the utilization of hardware parameters such as slices, LUTs, flip-flops, memory, input/output blocks, and timing information for Virtex-5 FPGA synthesis before the chip fabrication. The information is extracted for 8-bit to 128-bit key and grid data with initial parameters. TACIT security chip supports 400 MHz frequency for 128-bit key. The research work is an effort to provide the solution for the industries working towards embedded hardware security for the smart grid, power plants, and nuclear applications.

• The Journal of The Korea Institute of Intelligent Transport Systems
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• v.16 no.3
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• pp.83-94
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• 2017

There is a two lane ECTS(Electronic Toll Collection System) that users can pass with 80kph high speed in SeoBusan Tall Gate. This system to be combined two hi-pass lanes for removing meddle-island have been operated successfully. But, the appearance of two Lane ETCS makes toll gate more complicated, so it is very important how to arrange effectively various tolling lanes. This study was trying to evaluate lane configuration for minimizing speed and speed deviation among all kinds of lanes including two Lane ETCS in seoul toll gate. That is, we selected all scenarios to be happened actually, and evaluated them using micro traffic simulation model (VISSIM). The results of this study showed that each alternative had a very different speed and speed deviation by lane each other, so we will be able to achieve effective operation and configuration of lanes in toll gate using scenario methodology.

• Journal of Navigation and Port Research
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• v.26 no.5
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• pp.529-535
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• 2002

Design and implementation methodologies on the performance evaluation system of Two-Channel Ring-Core Flux-Gate Compass (TCRC FG-Compass) are described, with evaluation procedures and methods based on the polynomial regression models. Performance evaluation system consists of a step motor driving unit, a bearing transmitting unit and evaluation programs derived from polynomial regression formulae. Newly designed performance evaluation system enabled the accuracy of TCRC FG-Compass to be ascertained. It was confirmed that the size of residual deviation of TCRC FG-Compass is $2^{\circ}$, while that of the conventional one is $4^{\circ}$. In addition, the design methodology to the self estimation and correction of residual deviations is also discussed.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.12 no.5
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• pp.2317-2321
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• 2011

This paper is proposed new data crytoblock algorithm based on the private key cryptoalgorithim with existed other cryptography algorithims. Therefore new crytoblock design and simulation using the common Synopsys and ALTERA Max+ PlusII Ver.10.1. As a simulation result, new data crytoblock have gate counting 640Mbps at the 40M hz. We thought that proposed new data crytoblock adapt real time information security.