• Journal of the Korea Institute of Information Security & Cryptology
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• v.22 no.3
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• pp.495-504
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• 2012

This paper presents various speed optimization techniques for software implementation of the HIGHT block cipher on CPUs and GPUs. We considered 32-bit and 64-bit operating systems for CPU implementations. After we applied the bit-slicing and byte-slicing techniques to HIGHT, the encryption speed recorded 1.48Gbps over the intel core i7 920 CPU with a 64-bit operating system, which is up to 2.4 times faster than the previous implementation. We also implemented HIGHT on an NVIDIA GPU equipped with CUDA, and applied various optimization techniques, such as storing most frequently used data like subkeys and the F lookup table in the shared memory; and using coalesced access when reading data from the global memory. To our knowledge, this is the first result that implements and optimizes HIGHT on a GPU. We verified that the byte-slicing technique guarantees a speed-up of more than 20%, resulting a speed which is 31 times faster than that on a CPU.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 1996.04a
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• pp.587-591
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• 1996

Usually triangular patches are used to transfer geometric shape in Rpaid Prototyping CAM system. STL, a list of triangles, is de facto in RP industry. Because STL has no topology data, it can cause errornous results. So, STL should be verified before using. After adding support structures to anchor the part to the platform and to prevent sagging or distortion, slicing and layer by layer manufacturing process are done. But triangular patch is surface model and cannot provide dufficient information on geometry in the above processes. So, geometric modeling is necessary in verifying STL, adding support structures, and slicing. It is natural that triangle based modeling is the best when traingular patches are used as input. Considering support structures, solid and faces coexist in RP process. Therefore non-manifold modeler is required. In this study, triangle based non-manifold geometric modeling is proposed for RP system consitent with STL input.

• Journal of the military operations research society of Korea
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• v.14 no.1
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• pp.42-52
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• 1988

Many programmers start debugging by reading the faulty program from start to bottom without investigating carefully the erroneous program. Expert programmers, however, trace backward from a particular variable in a specific statement to identify all possible sources of influence on the value of variable (program slice). Weiser proposed a slicing algorithm (method) that is complex, iterative and still in modification [3,4]. This paper presents a method to generate a program slice by use of matrix computation which represents all possible slices of the program. The matrix representation of a program is soundly based on the graph theory of data dependency.

• Journal of the military operations research society of Korea
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• v.13 no.2
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• pp.42-52
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• 1987

Many programmers start debugging by reading the faulty program from start to bottom without investigating carefully the erroneous program. Expert programmers, however, trace backward from a particular variable in a specific statement to identify all possible sources of influence on the value of variable (program slice). Weiser proposed a slicing algorithm (method) that is complex, iterative and still in modification [3,4]. This paper presents a method to generate a program slice by use of matrix computation which represents all possible slices of the program. The matrix representation of a program is soundly based on the graph theory of data dependency.

• Journal of information and communication convergence engineering
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• v.17 no.3
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• pp.185-190
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• 2019

The explosive growth of data traffic and services has created cost challenges for networks. Studies have attempted to effectively apply network slicing in fifth generation networks to provide high speed, low latency, and various compatible services. However, in network slicing using mixed-integer linear programming, the operation count increases exponentially with the number of physical servers and virtual network functions (VNFs) to be allocated. Therefore, we propose an efficient slice allocation method based on cluster technology, comprising the following three steps: i) clustering physical servers; ii) selecting an appropriate cluster to allocate a VNF; iii) selecting an appropriate physical server for VNF allocation. Solver runtimes of the existing and proposed methods are compared, under similar settings, with respect to intra-slice isolation. The results show that solver runtime decreases, by approximately 30% on average, with an increase in the number of physical servers within the cluster in the presence of intra-slice isolation.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.11A
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• pp.1081-1091
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• 2005

Unlike conventional DVB-T transmission with the streaming method, DVB-H system based on the IPDC(IP Data Casting) method uses Time-slicing scheme to achieve the maximization of portability by reducing the power consumption of a receiver. To enhance the power efficiency of the receiver, Time-slicing scheme controls the receiver operation to perform only for corresponding burst in specific time slot. The additional power saving can also be achieved by reducing the required time for synchronization. In this paper, we propose a fast scattered pilot synchronization algorithm, which detects the pilot pattern of currently received OFDM symbol. The proposed scheme is based on the correlation between the adjacent subcarriers of potential scattered pilot position in two consecutively received OFDM symbols. Therefore, it can reduce the time for the scattered pilot synchronization within two symbols as com-pared with the conventional method used for DVB-T. And the proposed algorithm has better performance than the two schemes proposed by Nokia for DVB-H and the method using correlation with reference signal. Extensive com-puter simulation is performed based on ETSI EN300 744 ETSI and performance results show that the proposed algorithm has more efficient and stable operation than the conventional schemes.

• Journal of Digital Convergence
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• v.17 no.12
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• pp.197-202
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• 2019

In line with the era of the 4th Industrial Revolution, 5G technology has become common technology, and 5G technology is evaluated as a technology that minimizes the speed and response speed compared to 4G using technologies such as network slicing and ultra-multiple access. 5G NR stands for 5G mobile communication standard, and network slicing cuts the network into parallel connections to optimize the network. In addition, the risk of hacking is increasing as data is processed in the base station unit. In addition, since the number of accessible devices per unit area increases exponentially, there is a possibility of base station attack after hacking a large number of devices in the unit area. To solve this problem, this study proposes the introduction of quantum cryptography and 5G security standardization.

• Proceedings of the IEEK Conference
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• 2000.06b
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• pp.68-71
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• 2000

In this paper, we have measured the oxygen contents by FTIR in silicon wafer various process technology(slicing, lapping, polishing). The measured data are also compared with the data of etching process(KOH, Bright etching). Also we have measured the surface morpology in backside silicon wafer after etching treatment and etch pit density due to OISF after 4 step high temperature annealing process with optical microscope.

• Korean Journal of Remote Sensing
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• v.3 no.2
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• pp.81-87
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• 1987

The study was to analysis the dispersion of the cooling water of Kori atomic power station using thermal infrared data. The dispersion pattern of the cooling water analysis clearly on the LANDSAT TM band 6. It was changed due to tidal current, that is, the cooling water disperses north-eastern direction during the low tide and southweatern direction during the high tide. The relative temperature distribution was mapped through the density slicing method on the images.

• Korean Journal of Computational Design and Engineering
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• v.2 no.3
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• pp.195-210
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• 1997

In Rapid Prototyping process, the time required to build multiple prototype parts can be reduced by packing several parts optimally in a work volume. Interactive arrangement of the multiple parts is a tedious process and does not guarantee the optimal placement of all the parts. In this case, packing is a kind of 3-D nesting problem because parts are represented by STL files with 3-D information. 3-D nesting is well known to be a problem requiring an intense computation and an efficient algorithm to solve the problem is still under investigation. This paper proposes that packing 3-D parts can be simplified into a 2-D irregular polygon nesting problem by using the characteristic of rapid prototyping process that the process uses 2-dimensional slicing data of the parts and that slice of the STL parts are composed of polygons. Our algorithm uses no-fit-polygon (NFP) to place each slice without overlapping other slices in the same z-level. The allowable position of one part at a fixed orientation for given parts already packed can be determined by obtaining the union of all NFP's that are obtained from each slice of the part. Genetic algorithm is used to determine the order of parts to be placed and orientations of each part for the optimal packing. Optimal orientation of a part is determined while rotating it about the axis normal to the slice by finite angles and flipping upside down. This algorithm can be applied to any rapid prototyping process that does not need support structures.