• Transactions of the Korean Society of Mechanical Engineers B
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• v.38 no.11
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• pp.925-933
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• 2014

Today, computational fluid dynamics (CFD) is widely used in industry because of the availability of high-performance computers. However, full-scale analysis poses problems owing to the limited resources and time. In this study, the performance and optimal size of a heat exchanger were calculated using the effectiveness-number of transfer units (${\varepsilon}-NTU$) method and a database of characteristics heat exchanger. Information about the geometry and performance of various heat exchangers is collected, and the performance of the heat exchanger is calculated under the given operating conditions. To determine the optimal size of the heat exchanger, a Genetic Algorithm (GA) is used, and MATLAB and REFPROP are used for the calculation.

• Smart Media Journal
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• v.8 no.2
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• pp.9-15
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• 2019

Since the computational complexity for hologram generation increases exponentially with respect to the size of the point cloud, parallel processing using CUDA and/or OpenCL library based on multiple GPUs has recently become popular. The CUDA kernel for parallelization needs to consist of threads, blocks, and grids properly in accordance with the number of cores and the memory size in the GPU. In addition, in case of multiple GPU environments, the distribution in grid-by-grid, in block-by-block, or in thread-by-thread is needed according to the number of GPUs. In order to evaluate the performance of CGH generation, we compared the computational speed in CPU, in single GPU, and in multi-GPU environments by gradually increasing the number of points in a point cloud from 10 to 1,000,000. We also present a memory structure design and a calculation method required in the CUDA-based parallel processing to accelerate the CGH (Computer Generated Hologram) generation operation in multiple GPU environments.

• Journal of Digital Convergence
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• v.19 no.6
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• pp.233-238
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• 2021

Recently, blockchain technology accumulates and stores all transactions. Therefore, in order to verify the contents of all transactions, the data itself is compressed, but the scalability is limited. In addition, since a separate verification algorithm is used for each type of transaction, the verification burden increases as the size of the transaction increases. Existing blockchain cannot participate in the network because it does not become a block sink by using a server with a low specification. Due to this problem, as the time passes, the data size of the blockchain network becomes larger and it becomes impossible to participate in the network except for users with abundant resources. Therefore, in this paper, we are improved transaction as studied the zero knowledge proof algorithm for general operation verification. In this system, the design of zero-knowledge circuit generator capable of general operation verification and optimization of verifier and prover were also conducted.

• Environmental and Resource Economics Review
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• v.15 no.3
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• pp.505-530
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• 2006

For the district heating and cooling business, it is required to install energy-saving facilities using energy from waste and land fill gases such as combined heat and power(CHP). The current issues that this business faces can be summarized as below: which facilities including CHP can be economically introduced and how much of their capacities should be. Most of such issues are clearly related to the optimal plant design of the district heating and cooling business, and the prices of energy services such as heating and cooling energy, and electricity. The purpose of this study is to establish linear program model of least cost function and to practice the empirical test on a assumed district heating and cooling business area. The model could choose the optimal type of energy-producing facilities among various kinds available such as CHP's, absorption chillers, the ice-storage system, etc. CHP with the flexible heat and power ratio is also in the set of available technologies. And the model show us the optimal ration of heat producing facilities between CHP and historical heat only boiler in the service area. Some implications of this study are summarized as below. Firms may utilize this model as a tool for the analysis of their optimal size of the facilities and operation. Also, the government may refer the results to regulate resonable size of business.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.6A
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• pp.634-639
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• 2006

In this paper an MMIC 2-stage power amplifier is designed and fabricated for 5GHz wireless LAN applications using $0.5{\mu}m$ gate length PHEMT transistors. The PHEMT gate width is optimized in order to meet the linearity and efficiency of the MMIC power amplifier. The $0.5{\mu}m\times600{\mu}m$ PHEMT for the drive stage and $0.5{\mu}m\times3000{\mu}m$ PHEMT for the amplification stage are the optimized sizes to achieve more than 25dBc of third order IMD at the power level of 3dB back-off from the input P1dB and more than 22dBm output power under a supply voltage of 3.3V. The two-stage MMIC power amplifier is designed to be used for the both of HIPERLAN/2 and IEEE 802.11a because of its broadband characteristics. The fabricated PHEMT MMIC power amplifier exhibits a 20.1dB linear power gain, a maximum 22dBm output power, a 24% power added efficiency under 3.3V supply voltage. The input and output on-chip matching circuits are included on a chip of $1400\times1200{\mu}m^2$.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.17 no.8
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• pp.582-594
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• 2016

Most studies on hybrid buses are on large-sized buses and not mid-sized low-floor buses. This study uses MATLAB simulation to evaluate the fuel efficiency of such buses powered by diesel. Based on the results, a hybrid electric vehicle system is recommended for the best combination of power and gear ratio. A parallel hybrid system was selected for the hybridization, which transmits front and rear wheel power independently. The necessary power to satisfy the target performance was calculated, and the applicable capacity area was designed. Dynamic programing was used to create and optimize a component sizing algorithm, which was used to scale the capacity of each component of the power source to satisfy the design criteria. The fuel efficiency rate, optimum power source capacity, and gear ratio can be improved by converting a conventional bus into a parallel hybrid bus.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.25 no.11
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• pp.1627-1634
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• 2021

This paper introduces a low-power compact ADC circuit for analog Convolutional filter for low-power neural network accelerator SOC. While convolutional neural network accelerators can speed up the learning and inference process, they have drawback of consuming excessive power and occupying large chip area due to large number of multiply-and-accumulate operators when implemented in complex digital circuits. To overcome these drawbacks, we implemented an analog convolutional filter that consists of an analog multiply-and-accumulate arithmetic circuit along with an ADC. This paper is focused on the design optimization of a low-power 8bit SAR ADC for the analog convolutional filter accelerator We demonstrate how to minimize the capacitor-array DAC, an important component of SAR ADC, which is three times smaller than the conventional circuit. The proposed ADC has been fabricated in CMOS 65nm process. It achieves an overall size of 1355.7㎛², power consumption of 2.6㎼ at a frequency of 100MHz, SNDR of 44.19 dB, and ENOB of 7.04bit.

• Journal of the Microelectronics and Packaging Society
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• v.17 no.4
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• pp.49-60
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• 2010

Semiconductor packages are increasingly moving toward miniaturization, lighter and high performance. Futhermore, packages become thinner. Thin packages will generate serious reliability problems such as warpage, crack and other failures. Reliability problems are mainly caused by the CTE mismatch of various package materials. Therefore, proper selection of the package materials and geometrical optimization is very important for controlling the warpage and the stress of the package. In this study, we investigated the characteristics of the warpage and the stress of several packages currently used in mobile devices such as CABGA, fcSCP, SCSP, and MCP. Warpage and stress distribution are analyzed by the finite element simulation. Key material properties which affect the warpage of package are investigated such as the elastic moduli, CTEs of EMC molding and the substrate. Geometrical effects are also investigated including the thickness or size of EMC molding, silicon die and substrate. The simulation results indicate that the most influential factors on warpage are EMC molding thickness, CTE of EMC, elastic modulus of the substrate. Simulation results show that warpage is the largest for SCSP. In order to reduce the warpage, DOE optimization is performed, and the optimization results show that warpage of SCSP becomes $10{\mu}m$.

• Applied Chemistry for Engineering
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• v.32 no.3
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• pp.320-325
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• 2021

In this study, an optimization for the production of water emulsion was designed by adding an extract of wheat sprout, which is known to contain a large amount of antioxidants. The central composite design of reaction surface analysis method (CCD-RSM) was used for the optimization process. The amount of emulsifier, emulsification time, and added amount of wheat sprout extract were selected as independent variables based on our preliminary experiments. The mean droplet size (MDS), viscosity, and emulsion stability index (ESI) were set as the responses to evaluate the stability of the emulsion. For each independent variable, the P-value and coefficient of determination were evaluated to verify the reliability of the experiments. From the result of CCD-RSM, optimum conditions for the emulsification were determined as 23.6 min, 7.7 wt.%, and 3.9 wt.% for the emulsification time, amount of emulsifier, and amount of sprout, respectively. From the optimized condition obtained, MDS, viscosity, and ESI after 7 days from reaction were estimated as 252.3 nm, 616.7 cP, and 88.7%, respectively. The overall satisfaction was 0.9137, which supported the validity of the experiments, and the error rate was measured at 0.5% or less by advancing the experiments. Therefore, an optimized process for producing an emulsion by adding the malt extract was designed by the CCD-RSM.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.4B
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• pp.771-782
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• 2000

In this paper, an H.263 video codec is implemented by adopting the concept of hardware and software co-design. Each module of the codec is investigated to find which approach between hardware and software is better to achieve real-time processing speed as well as flexibility. The hardware portion includes motion-related engines, such as motion estimation and compensation, and a memory control part. The remaining portion of theH.263 video codec is implemented in software using a RISC processor. This paper also introduces efficient design methods for hardware and software modules. In hardware, an area-efficient architecture for the motion estimator of a multi-resolution block matching algorithm using multiple candidates and spatial correlation in motion vector fields (MRMCS), is suggested to reduce the chip size. Software optimization techniques are also explored by using the statistics of transformed coefficients and the minimum sum of absolute difference (SAD)obtained from the motion estimator.