• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2001.04a
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• pp.1-7
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• 2001

This paper presents product level considerations for multichip packaging as a cost effective alternative to single chip packaging in the design and manufacture of mobile telephony products. Important aspects include component functionality and complexity, acquisition and logistics costs, product modularity and integration. Multichip packaging offers unique solutions and significant system level cost savings in many applications including RF modules, digital matrix functions and product options such as security, data storage, voice recognition, etc.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 1993.06a
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• pp.921-924
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• 1993

For the purpose of applying to a high-speed control system, such as engine control for automobile application, we propose an architecture of a fuzzy inference processor, which can realize high-speed inference, high-resolution, and can be implemented with small chip area. We have designed a single chip based on the architecture, and confirmed the performance, such as 140 kFLIPS with 8-bit resolution.

• Proceedings of the Korean Institute of Communication Sciences Conference
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• 2004.07a
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• pp.326-326
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• 2004

• Transactions of the Korean Society for Noise and Vibration Engineering
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• v.16 no.12 s.117
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• pp.1272-1278
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• 2006

This paper presents a novel MEMS condenser microphone with rigid backplate to enhance acoustic characteristics. The MEMS condenser microphone consists of membrane and backplate chips which are bonded together by gold-tin(Au/Sn) eutectic solder bonding. The membrane chip has $2.5mm{\times}2.5mm$, 0.5${\mu}m$ thick low stress silicon nitride membrane, $2mm{\times}2mm$ Au/Ni/Cr membrane electrode, and 3${\mu}m$ thick Au/Sn layer. The backplate chip has $2mm{\times}2mm$, 150${\mu}m$ thick single crystal silicon rigid backplate, $1.8mm{\times}1.8mm$ backplate electrode, and air gap, which is fabricated by bulk micromachining and silicon deep reactive ion etching. Slots and $50{\sim}60{\mu}m$ radius circular acoustic holes to reduce air damping are also formed in the backplate chip. The fabricated microphone sensitivity is 39.8 ${\mu}V/Pa$(-88 dB re. 1 V/Pa) at 1 kHz and 28 V polarization voltage. The microphone shows flat frequency response within 1 dB between 20 Hz and 5 kHz.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.10
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• pp.186-194
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• 1996

The SliM (sliding memory plane) array processor has been proposed to alleviate disadvantages of existing mesh-connected SIMD(single instruction stream- multiple data streams) array processors, such as the inter-PE(processing element) communication overhead, the data I/O overhead and complicated interconnections. This paper presents the deisgn and implementation of SliM image processor ASIC (application specific integrated circuit) chip consisting of mesh connected 5 X 5 PE. The PE architecture implemented here is quite different from the originally proposed PE. We have performed the front-end design, such as VHDL (VHSIC hardware description language)modeling, logic synthesis and simulation, and have doen the back-end design procedure. The SliM ASIC chip used the VTI 0.8$\mu$m standard cell library (v8r4.4) has 55,255 gates and twenty-five 128 X 9 bit SRAM modules. The chip has the 326.71 X 313.24mil$^{2}$ die size and is packed using the 144 pin MQFP. The chip operates perfectly at 25 MHz and gives 625 MIPS. For performance evaluation, we developed parallel algorithms and the performance results showed improvement compared with existing image processors.

• Journal of Microbiology and Biotechnology
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• v.22 no.2
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• pp.226-229
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• 2012

Bacterial hemoglobin from Vitreoscilla (VHb) is recognized as a good fusion protein for the soluble expression of foreign protein. In this study, we generated a monoclonal antibody (MAb) against VHb for its detection. For the rapid screening of MAb, a protein chip technology based on the Alexa-488 (A488) dye labeling method was introduced. In order to fabricate the chip, the VHb protein was chemically coupled to the chip surface and then the culture supernatants of 84 hybridoma cell lines were spotted onto the VHb chip. The bound MAbs were measured by A488-modified anti-mouse IgG. A single spot (MAb A10) exhibited significantly high signal intensity. The immunoblot analysis evidenced that the MAb A10 can detect VHb-fused proteins with high specificity.

• JSTS:Journal of Semiconductor Technology and Science
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• v.4 no.4
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• pp.258-262
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• 2004

Storage over Ethernet (SoE) is a network storage architecture that allows direct attachment of existing ATA/ATAPI devices to Ethernet without a separate server. Unlike SAN, no server computer intervenes between the storage and the client hosts. We propose a SoE disk controller (SoEDC) amenable to low-cost, single-chip implementation that processes a simplified L3/L4 protocol and converts commands between Ethernet and ATA/ATAPI, while the rest of the complex tasks are performed by the remote hosts. Thanks to simple architecture and protocol, the SoEDC implemented on a single $4mm{\times}4mm$ chip in 0.18um CMOS technology achieves maximum throughput of 55MB/s on Gigabit Ethernet, which is comparable to that of a high-performance disk storage locally attached to a host computer.

• Asian-Australasian Journal of Animal Sciences
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• v.27 no.11
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• pp.1521-1525
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• 2014

This study investigated heritability for bovine growth estimated with genomewide single nucleotide polymorphism (SNP) information obtained from a DNA microarray chip. Three hundred sixty seven Korean cattle were genotyped with the Illumina BovineSNP50 BeadChip, and 39,112 SNPs of 364 animals filtered by quality assurance were analyzed to estimate heritability of body weights at 6, 9, 12, 15, 18, 21, and 24 months of age. Restricted maximum likelihood estimate of heritability was obtained using covariance structure of genomic relationships among animals in a mixed model framework. Heritability estimates ranged from 0.58 to 0.76 for body weights at different ages. The heritability estimates using genomic information in this study were larger than those which had been estimated previously using pedigree information. The results revealed a trend that the heritability for body weight increased at a younger age (6 months). This suggests an early genetic evaluation for bovine growth using genomic information to increase genetic merits of animals.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.909-912
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• 2005

According to miniaturization trend of rehabilitation medical equipment such as hearing aid, study to replace previous complex system with semiconductor SOC (System-on-Chip) chip becomes lively. In this study, after investigating of existent hearing aid performance in circuit design approach, low electric power consuming, single power supply (1.4V battery) CMOSS OP AMP was designed. Analog circuit design tools such as Hspice and Cadence were used for circuit simulation and implementing layout design. This study shows technical methods particularly for layout design. The work is done in pmos and nmos active element layout design in addition to passive element design such as resister, capacitor and inductor.

• Proceedings of the KIEE Conference
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• 1990.11a
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• pp.332-335
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• 1990

There are several methods in controlling resonant converters to regulate the output with low switching losses. In this paper, Pulse-width modulation method or current controlled method is applied to regulate the output with low switching losses. In digital implementation of resonant converter systems, the speed of the applied processor is very critical since the switching frequency is very high. Thus the various possible candidates of microprocessors are evaluated for the implementation of resonant converter systems. Then too design methods and techniques are desioribed when single chip processor is used to simplify hardware requirements.