• 한국전산유체공학회:학술대회논문집
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• 한국전산유체공학회 2004년도 추계 학술대회논문집
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• pp.173-176
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• 2004

In this study, the multidisciplinary aerodynamic-structural optimal design is carried out for the supersonic fighter wing. Through the aeroelastic analyses of the various candidate wings, the aerodynamic and structural performances are calculated such as the lift coefficient, the drag coefficient and the deformation of the wing. In general, the supersonic fighter is maneuvered under the various flight conditions and those conditions must be considered all together during the design process. The multi-point design, therefore, is deemed essential. For this purpose, supersonic dash, long cruise range and high angle of attack maneuver are selected as representative design points. Based on the calculated performances of the candidate wings, the response surfaces for the objectives and constraints are generated and the supersonic fighter wing is designed for better aerodynamic performances and less weights than the baseline. At each design point, the single-point design is performed to obtain better performances. Finally, the multi-point design is performed to improve the aerodynamic and structural performances for all design points. The optimization results of the multi-point design are compared with those of the single-point designs and analyzed in detail.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1999년도 추계학술대회 논문집 학회본부 B
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• pp.778-780
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• 1999

Arithmetic unit speed depends strongly on the algorithms employed to realize the basic arithmetic operations.(add, subtract multiply, and divide) and on the logic design. Recent advances in VLSI have increased the feasibility of hardware implementation of floating point arithmetic units and microprocessors require a powerful floating-point processing unit as a standard option. This paper describes the design of floating-point multiplier for IEEE 754-1985 Single-Precision operation. Booth encoding algorithm method to reduce partial products and a Wallace tree of 4-2 CSA is adopted in fraction multiplication part to generate the $32{\times}32$ single-precision product. New scheme of rounding and sticky-bit generation is adopted to reduce area and timing. Also there is a true sign generator in this design. This multiplier have been implemented in a ALTERA FLEX EPF10K70RC240-4.

• 대한기계학회논문집A
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• 제30권8호
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• pp.889-896
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• 2006

The concept of reliability has been applied to the topology optimization based on a reliability index approach or a performance measure approach. Since these approaches, called double-loop single vector approach, require the nested optimization problem to obtain the most probable point in the probabilistic design domain, the time for the entire process makes the practical use infeasible. In this work, new reliability-based topology optimization method is proposed by utilizing single-loop single-vector approach, which approximates searching the most probable point analytically, to reduce the time cost. The results of design examples show that the proposed method provides efficiency curtailing the time for the optimization process and accuracy satisfying the specified reliability.

• 한국전산유체공학회:학술대회논문집
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• 한국전산유체공학회 2003년도 The Fifth Asian Computational Fluid Dynamics Conference
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• pp.240-242
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• 2003

A method for performing two-dimensional lift-constraint drag minimization in inviscid compressible flows on unstructured meshes is developed. Sensitivities of objective function with respect to the design variables are efficiently obtained by using a continuous adjoint method. In addition, parallel algorithm is used in multi-point design optimization to enhance the computational efficiency. The characteristics of single-point and multi-point optimization are examined, and the comparison of these two method is presented.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 추계종합학술대회 논문집(2)
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• pp.301-304
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• 2000

In this paper, we designed a 256-point FFT processor using VHDL. We adopted Radix-2$^2$SDC(Single-path Delay Commutator) architectures to reduce the number of complex multipliers. We confirmed the operation of the design through simulation using Altera MAX+PLUS II.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2010년도 춘계학술대회 논문집
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• pp.1115-1116
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• 2010

• 한국항공우주학회지
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• 제42권9호
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• pp.773-778
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• 2014

항공기에 있어서 통신장비는 조종사간 내부통신과 타항공기 및 지상관제탑과의 외부통신을 가능케하는 장비로서 임무 수행 및 안전에 있어서 매우 중요하다. 따라서 송수신 기능의 구현만으로는 요구되는 성능요구조건을 만족했다고 할 수 없고, 잡음이 없는 맑고 깨끗한 통신품질을 제공해야 한다. 본 논문에서는 T-50 항공기(고등훈련기) 운용 중에 발생된 내부통신 잡음 현상에 대한 원인을 분석하고, 이 현상에 대한 개선을 위해 Single Point Ground 설계 개념을 적용한 결과를 정리하였다. 또한 설계 개선사항에 대한 검증을 위한 비행시험 결과를 함께 기술하였다.

• 한국전산구조공학회논문집
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• 제18권1호
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• pp.51-59
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• 2005

SLSV(single loop single vector)방법은 신뢰성기반 최적설계(reliability-based design optimization, RBDO)에서 중첩된 반복과정을 제거함으로써 최적설계의 과도한 계산비용 문제에 대한 해결책을 제시하고 있지만, 종종 수렴하지 못하거나 잘못된 해가 얻어지는 등의 불안정성, 부정확성 문제를 가지고 있어 그 활용이 제한적이다. 본 논문에서는 수정된 HMV(hybrid mean value)방법, Inactive Design, Active MPP(most probable point) Design의 적용을 통해 SLSV방법에 있어서 안정성과 효율성을 효과적으로 개선시킬 수 있는 수정된 SLSV방법을 제안하였고 또한 다양한 예제를 통해 수정된 SLSV방법의 유용성을 검증하였다.

• 대한전자공학회논문지SD
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• 제48권10호
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• pp.72-81
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• 2011

본 논문에서는 IEEE754 표준의 단정도 및 배정도를 지원하는 새로운 부동소수점 변환기를 제안하고 설계하였다. 제안된 변환기는 부호 있는 정수(32비트/64비트)와 부동소수점(단정도/배정도) 간 변환, 부호 없는 정수(32비트/64비트)를 부동소수점(단정도/배정도)으로의 변환, 부동소수점 단정도와 배정도 간 변환뿐만 아니라 부호 있는 고정소수점(32비트 64비트)과 부동소수점(단정도 배정도) 간 변환을 지원한다. 모든 입력 형태를 하나의 형태로 만드는 새로운 내부 형태를 정의함으로써 출력 형태의 표현 범위에 따른 오버플로우 검사를 쉽게 하도록 하였다. 내부 형태는 IEEE754 2008 표준에서 정의된 부동소수점 배정도의 확장된 형태(extended format)와 유사하다. 이 표준에서는 부동소수점 배정도의 확장된 형태(extended format)의 최소 지수부 비트폭은 15비트라고 명시하지만 제안된 컨버터를 구현하는데 11비트만으로도 충분하다. 또한 덧셈기가 대신 +1 증가기를 사용하면서 라운딩 연산과 음수의 정확한 표현이 가능하도록 변환기의 라운딩 스테이지를 최적화하였다. 단일 클럭 사이클 데이터패스와 5단 파이프라인 데이터패스를 설계하였다. 변환기의 두 데이터패스에 대한 HDL 모델을 기술한 후에 Synopsys design compiler를 사용하여 TSMC 180nm 공정 라이브러리로 합성하였다. 합성 결과의 셀 면적은 12,886 게이트(2입력 NAND 게이트 기준)이고 최대 동작 주파수는 411MHz이다.

• Journal of Power Electronics
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• 제11권2호
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• pp.218-227
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• 2011

The subject of variable step size maximum power point tracking (MPPT) algorithms has been addressed in the literature. However, most of the addressed algorithms tune the variable step size according to two variables: the photovoltaic (PV) array voltage ($V_{PV}$) and the PV array current ($I_{PV}$). Therefore, both the PV array current and voltage have to be measured. Recently, maximum power point trackers that arc based on a single variable ($I_{PV}$ or $V_{PV}$) have received a great deal of attention due to their simplicity and ease of implementation, when compared to other tracking techniques. In this paper, two methods have been proposed to design a variable step size MPPT algorithm using only a single current sensor for stand-alone battery storage PV systems. These methods utilize only the relationship between the PV array measured current and the converter duty cycle (D) to automatically adapt the step change in the duty cycle to reach the maximum power point (MPP) of the PV array. Detailed analyses and flowcharts of the proposed methods are included. Moreover, a comparison has been made between the proposed methods to investigate their performance in the transient and steady states. Finally, experimental results with field programmable gate arrays (FPGAs) are presented to verify the performance of the proposed methods.