Proceedings of the IEEK Conference (대한전자공학회:학술대회논문집)

The Institute of Electronics and Information Engineers (대한전자공학회)
권호 표지

Design of a 256-point FFT Processor

Pipeline 방식 256-point FFT Processor의 설계

  • Published : 2000.11.01
Download PDF
⟨ Previous Next ⟩

Abstract

In this paper, we designed a 256-point FFT processor using VHDL. We adopted Radix-2$^2$SDC(Single-path Delay Commutator) architectures to reduce the number of complex multipliers. We confirmed the operation of the design through simulation using Altera MAX+PLUS II.

Keywords