• Proceedings of the KSME Conference
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• 2003.11a
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• pp.1027-1032
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• 2003

Thermo-mechanical behavior of flip-chip plastic ball grid array (FC-PBGA) packages are characterized by high sensitive $Moir{\acute{e}}$ interferometry. $Moir{\acute{e}}$ fringe patterns are recorded and analyzed for several temperatures. Deformation analysis of bending displacements of the packages and average strains in the solder balls for a single-sided package assembly and a double-sided package assembly are presented. The bending displacement of the double-sided package assembly is smaller than that of the single-sided one. The largest of effective strain occurred in the solder ball located at the edge of the chip and its magnitude of the double-sided package assembly is greater than that of single-sided one.

• Journal of the Microelectronics and Packaging Society
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• v.19 no.4
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• pp.45-50
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• 2012

A family of multi-die DRAM packages was developed that incorporate the full functionality of an SODIMM into a single package. Using a common ball assignment analogous to the edge connector of an SODIMM, a broad range of memory types and assembly structures are supported in this new package. In particular DDR3U, LPDDR3 and DDR4RS are all supported. The center-bonded DRAM use face-down wirebond assembly, while the peripherybonded LPDDR3 use the face-up configuration. Flip chip assembly as well as TSV stacked memory is also supported in this new technology. For the center-bonded devices (DDR3, DDR4 and LPDDR3 ${\times}16$ die) and for the face up wirebonded ${\times}32$ LPDDR3 devices, a simple manufacturing flow is used: all die are placed on the strip in a single machine insertion and are sourced from a single wafer. Wirebonding is also a single insertion operation: all die on a strip are wirebonded at the same time. Because the locations of the power signals is unchanged for these different types of memories, a single consolidated set of test hardware can be used for testing and burn-in for all three memory types.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2012.10a
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• pp.343-344
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• 2012

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.23 no.12
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• pp.973-977
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• 2010

The temperature of junction in LED affects the life time and performance. however, the measurement of junction temperature in module is very difficult. In this paper, to measure the junction temperature in LED module, optical and electrical properties is measured in single package in temperature from 25 [$^{\circ}C$] to 85 [$^{\circ}C$], and then junction temperature can is estimated in module with measuring the average voltage of single package. As results, the junction temperature of single package is measured the temperature of 61.2 [$^{\circ}C$] in ambient temperature, also, the junction temperature of LED module is measured the temperature of 72.5 [$^{\circ}C$] in ambient temperature.

• Korean Management Science Review
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• v.25 no.1
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• pp.55-74
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• 2008

In recent warfare, the performance improvement of air weapon systems enables an aircraft to strike multiple targets on a single sortie. Further, aircrafts attacking targets may carry out an operation as a strike package that is composed of bombers, escort aircrafts, SEAD (Suppression of Enemy Air Defenses) aircrafts and etc. In this paper, we present an aircraft allocation model that allocates multiple targets to a single sortie in the form of a strike package. A mixed integer programming is developed and solved by using a commercially available software. The new model is better than existing ones because not only it allocates aircrafts to multiple targets but also it models the concept of the strike package. We perform a computational experiment to compare the result of the new model with that of existing ones, and perform sensitivity analysis by varying a couple of important parameters.

• Journal of the Microelectronics and Packaging Society
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• v.25 no.4
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• pp.59-66
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• 2018

In this paper, we analyzed the usefulness of single-structured printed circuit board (PCB) modeling by using numerical analysis to model the PCB structure applied to a package for semiconductor purposes and applying modeling assuming a single structure. PCBs with circuit layer of 3rd and 4th were used for analysis. In addition, measurements were made on actual products to obtain material characteristics of a single structure PCB. The analysis results showed that if the PCB was modeled in a single structure compared to a multi-layered structure, the warpage analysis results resulting from modeling the PCB structure would increase and there would be a significant difference. In addition, as the circuit layer of the PCB increased, the mechanical properties of the PCB, the elastic coefficient and inertia moment of the PCB increased, decreasing the package's warpage.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2000.04a
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• pp.3-7
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• 2000

In summary, a fundamentally new paradigm called System-on-Package could potentially become a complementary alternative to System-on-Chip, thus providing a balanced set of system-level functions between the semiconductor IC and single component package beyond the year 2007. The concurrent engineering and optimization of IC and package could overcome the fundamental IC issues presented above.

• Journal of the Microelectronics and Packaging Society
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• v.24 no.4
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• pp.91-95
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• 2017

Package-On-Package (PoP) technology is developing toward smaller form factors with high-speed data transfer capabilities to cope with high DDR4x memory capacity. The common application processor (AP) used for PoP devices in smartphones has the bottom package as logic and the top package as memory, which requires both thermally and electrically enhanced functions. Therefore, it is imperative that PoP designs consider both thermal and power distribution network (PDN) issues. Stacked packages have poorer thermal dissipation than single packages. Since the bottom package usually has higher power consumption than the top package, the bottom package impacts the thermal budget of the top package (memory). This paper investigates the thermal and electrical characteristics of PoP designs, particularly the bottom package. Findings include that via and dense via-cluster volume have an important role to lower thermal resistance to the motherboard, which can be an effective way to manage chip hot spots and reduce the thermal impact on the memory package. A Cu block and dense via-cluster layout with an optimal location are proposed to drain the heat from the chip hot spots to motherboard which will enhance thermal and electrical performance at the design stage. The analytical thermal results can be used for design guidelines in 3D packaging.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.07a
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• pp.32-35
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• 2002

The work focuses on the development of a Cu lead-frame with a single-sided adhesive tape for cost reduction and reliability improvement of LOC (lead on chip) package products, which are widely used for the plastic-encapsulation of memory chips. Most of memory chips are assembled by the LOC packaging process where the top surface of the chip is directly attached to the area of the lead-frame with a double-sided adhesive tape. However, since the lower adhesive layer of the double-sided adhesive tape reveals the disparity in the coefficient of thermal expansion from the silicon chip by more than 20 times, it often causes thermal displacement-induced damage of the IC pattern on the active chip surface during the reliability test. So, in order to solve these problems, in the resent work, the double-sided adhesive tape is replaced by a single-sided adhesive tape. The single-sided adhesive tape does net include the lower adhesive layer but instead, uses adhesive materials, which are filled in clear holes of the base film, just for the attachment of the lead-frame to the top surface of the memory chip. Since thermal expansion of the adhesive materials can be accommodated by the base film, memory product packaged using the lead-flame with the single-sided adhesive tape is shown to have much improved reliability. Author allied this invention to the Korea Patent Office for a patent (4-2000-00097-9).

• Journal of the Microelectronics and Packaging Society
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• v.13 no.4
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• pp.17-25
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• 2006

Thermo-mechanical behavior of flip-chip plastic ball grid array (FC-PBGA) packages are characterized by high sensitive $moir\'{e}$ interferometry. $Moir\'{e}$ fringe patterns are recorded and analyzed for several temperatures. Deformation analysis of bending displacements of the packages and average strains in the solder balls for both single and double-sided package assemblies are presented. The bending displacement of the double-sided package assembly is smaller than that of the single-sided one because of its symmetric structure. The largest effective strain occurred at the solder ball located on the edge of the chip and its magnitude of the double-sided package assembly is greater than that of single-sided one by 50%.