• Journal of the Korea Academia-Industrial cooperation Society
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• v.5 no.5
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• pp.429-432
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• 2004

In this paper, we propose a new sorting algorithm for ATM switch with a shared buffer which has a sequencer architecture with single queue. The proposed switch performs a sorting procedure of ATM cell based on the output port number of ATM cell with hardware implementation. The proposed architecture has a single buffer physically but logically it has function of multi-queue which is designed at most to control the conflicts in output port. In the future, this architecture will take various applications for routing switch and has flexibility for the extension of system structure. therefore, this structure is expected on good structure in effective transmission.

• IE interfaces
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• v.13 no.3
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• pp.424-430
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• 2000

Supply chain management (SCM) is an area that has recently received a great deal of attention in the business community. While SCM is relatively new, the idea of coordinated planning is not. During the last decades, many researchers have investigated multi-stage inventory problems. However, only a few papers address the problem of cost-optimal coordination of multi-stage inventory control with respect to service measures. Even published approaches have a shortcoming in dealing with a delivery lead time consisted of a shipping time and a waiting time. Assumed that there is no waiting time, or that the delivery lead time is implicitly compounded of a shipping time and a waiting time, the problem is often simplified into a multi-stage buffer allocation and a single-stage stochastic buffer sizing problem at all installations. This paper presents a simulation-based heuristic algorithm and a comparison with others for the problem that cannot be decomposed into a multi-stage buffer allocation and a single-stage stochastic buffer sizing problem because the waiting time ties together all stages. The comparison shows that the simulation-based heuristic algorithm performs better than other approaches in saving average inventory cost for both Poisson and Normal demands.

• IEIE Transactions on Smart Processing and Computing
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• v.5 no.3
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• pp.207-214
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• 2016

Optical communication systems are rapidly spread following increases in data traffic. In this work, a 32-Gb/s inductorless output buffer circuit with adjustable pre-emphasis is proposed. The proposed circuit consists of an output buffer circuit and an emphasis circuit. The emphasis circuit emphasizes the high frequency components and adds the characteristics of the output buffer circuit. We proposed a design method using a small-signal equivalent-circuit model and designed the compensation characteristics with a 65-nm CMOS process in detail using HSPICE simulation. We also realized adjustable emphasis characteristics by controlling the voltage. To confirm the advantages of the proposed circuit and the design method, we fabricated an output buffer IC with adjustable pre-emphasis. We measured the jitter and eye height with a 32-Gb/s input using the IC. Measurement results of double-emphasis showed that the jitter was 14% lower, and the eye height was 59% larger than single-emphasis, indicating that our proposed configuration can be applied to the design of an output buffer circuit for higher operation speed.

• Archives of Pharmacal Research
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• v.23 no.3
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• pp.197-201
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• 2000

In an aqueous piperacillin sodium solution, a well-defined single wave or single peak was observed by direct current(DC) polarography or differential pulse polarography(DPP). The peak potential change per pH unit was -54 mV in the phosphate buffer at $18^{\circ}C$, which indicated that protons were involved in the electrochemical reduction of the 2,3-dioxopiperazine moiety of piperacillin sodium with a $H^{+}e^{-}$ ratio of one. Using a phosphate buffer of pH 4.3, the $1.0{times}10^{-7}$ M piperacillin sodium single peak could be determined by DPP with relative standard deviation of 1.6 %(n=3). Piperacillin sodium could be analyzed with-out interference from penicillin G-potassium, which enabled the employment of DPP as a fast and simple technique for monitoring the synthetic process of the antibiotic.

• Journal of KIISE:Databases
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• v.27 no.4
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• pp.549-561
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• 2000

In database management systems(DBMSs), partial rollback is a useful facility that cancels part of the executed operations upon user's requests without a total rollback. Many relational DBMSs(RDBMSs) provide this facility, However, object-orientccd DBMSs (OODBMSs) cannot utilize the previous recovery scl18lne of partial rollback usccd in (RDBMSs) since, unlike RDBMSs, they use a dual buffer consisting of an object buffer and a page buffer. Therefore, a new recovery scheme is required that rolls back the data efficiently in the dual buffer. We propose four partial rollback schemes in OODBMSs that use a dual buffer. We classify the proposed schemes into the single buffer based partial rollback scheme and the dual buffer based partial rollback scheme according to the number of buffers used for partial rollback processing. We further classify them into Uthe page buffer based partial rollback scheme, 2)the object buffccr based partial rollback scheme, 3)the dual buffer based partial rollback scheme using soft log, and 4)the dual buffer based partial rollback scheme using shadows. We evaluate the performance by mathematical analysis and experiments. The results show that the dual buffer based partial rollback scheme using shadows provides the best performance.

• Progress in Superconductivity
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• v.4 no.2
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• pp.127-131
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• 2003

We have designed and measured an SFQ(Single Flux Quantum) OR gate for a superconducting ALU (Arithmetic Logic Unit). To optimize the circuit, we used WRspice, XIC and Lmeter for simulations and layouts. The OR gate was consisted of a Confluence Buffer and a D Flip-Flop. When a pulse enters into the OR gate, the pulse does not propagate to the other input port because of the Confluence Buffer. A role of D Flip-Flip is expelling the data when the clock is entered into D Flip-Flop. For the measurement of the OR gate operation, we attached three DC/SFQs, three SFQ/DCs and one RS Flip -Flop to the OR gate. DC/SFQ circuits were used to generate the data pulses and clock pulses. Input frequency of 10kHz and 1MHzwere used to generate the SFQ pulses from DC/SFQ circuits. Output data from OR gate moved to RS flip -Flop to display the output on the oscilloscope. We obtained bias margins of the D Flip -Flop and the Confluence Buffer from the measurements. The measured bias margins $\pm$38.6% and $\pm$23.2% for D Flip-Flop and Confluence Buffer, respectively The circuit was measured at the liquid helium temperature.

• JSTS:Journal of Semiconductor Technology and Science
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• v.5 no.4
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• pp.262-269
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• 2005

Semiconductor scientists and engineers ideally desire the faster but the cheaper non-volatile memory devices. In practice, no single device satisfies this desire because a faster device is expensive and a cheaper is slow. Therefore, in this paper, we use heterogeneous non-volatile memories and construct an efficient hierarchy for them. First, a small RAM device (e.g., MRAM, FRAM, and PRAM) is used as a write buffer of flash memory devices. Since the buffer is faster and does not have an erase operation, write can be done quickly in the buffer, making the write latency short. Also, if a write is requested to a data stored in the buffer, the write is directly processed in the buffer, reducing one write operation to flash storages. Second, we use many types of flash memories (e.g., SLC and MLC flash memories) in order to reduce the overall storage cost. Specifically, write requests are classified into two types, hot and cold, where hot data is vulnerable to be modified in the near future. Only hot data is stored in the faster SLC flash, while the cold is kept in slower MLC flash or NOR flash. The evaluation results show that the proposed hierarchy is effective at improving the access time of flash memory storages in a cost-effective manner thanks to the locality in memory accesses.

• Journal of Navigation and Port Research
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• v.33 no.5
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• pp.331-337
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• 2009

Container crane is main equipment in container terminals and it determines the productivity and the efficiency of container terminals. The typical type of container cranes has the single trolley and one among advanced types of them has the dual trolley. The objective of this paper is to analyze the buffer size of a container crane with the dual trolley in container terminals. We present a simulation model for analysing the buffer space of a container crane with the dual trolley. The buffer space is located between main trolley in sea-side and second trolley in yard-side. We performs various simulation experiments and analyze the buffer size to estimate the required productivity.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.6 no.5
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• pp.703-717
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• 2002

This paper illustrates the implementation of a scalable shared buffer asynchronous transfer mode (ATM) switch. The designed shared buffer ATM switch has a shared buffet of a pipelined memory which has the access time of 4 ns. The high-speed buffer access time supports a possibility of the implementation of a shared buffer ATM switch which has a large switching capacity. The designed switch architecture provides flexible switching performance and port size scalability with the independence of queue address control from buffer memory control. The switch size and the buffer size of the designed ATM switch can be reconfigured without serious circuit redesign. The designed prototype chip has a shared buffer of 128-cell and 4 ${\times}$ 4 switch size. It is integrated in 0.6um, double-metal, and single-poly CMOS technology. It has 80MHz operating frequency and supports 640Mbps per port.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.11a
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• pp.115-115
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• 2009

Epitaxial ZnO film was grown on Si(111) substrate with oxidazed CrN buffer by plasma-assisted molecular beam epitaxy (PAMBE). The growth and structural properties are investigated. The single crystalline growth was revealed by in-situ RHEED analysis. Crystalline quality of ZnO film grown on oxidized CrN buffer was investigated by the X-ray rocking curves. The FWHMs of (0002) XRCs was $1.379^{\circ}$. This value was smaller than the ZnO film grown directly on (111) Si substrate.