• 한국초전도학회:학술대회논문집
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• v.10
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• pp.189-192
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• 2000

We fabricated rapid single-flux-quantum RS flip-flop circuits with and without Y$_1$Ba$_2$Cu$_3$O$_{7-{\delta}}$(YBCO) ground plane. The circuit consists of SNS-type ramp-edge Josephson junctions that have cobalt-doped YBCO and Sr$_2$AITaO$_6$(SAT) for barrier layer and insulator layer, respectively. The fabricated Josephson junction showed a typical RSJ-like current-voltage(I-V) characteristics above 50K. We sucessfuly demonstrated RS flip-flop at temperatures around 50K. The RS flip-flop fabricated on ground plane showed more definite set and reset state in voltage-flux(V-${\phi}$) modulation curve for read SQUID, which may be attributed to a shielding effect of the YBCO ground plane.

• Proceedings of the Materials Research Society of Korea Conference
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• 2010.05a
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• pp.30.2-30.2
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• 2010

Nano-scale p-n junction can generate various nano-scale functional devices such as nanowire light emitting diode, nanowire solar cell, and nanowire sensor. The core shell type nanowire p-n junction has been considered for the high efficient devices in many previous reports. On the other hand, although device efficiency is relatively lower, the cross bar type p-n junction has simple topological structure, suggested by C.M. Lieber group, to integrate easily many p-n junction devices in one board. In this study, for the integration of the cross bar nanowire p-n junction device, a simple fabrication route, employed dielectrophoretic array and direct printing techniques, was demonstrated by the successful fabrication and programmable integration of the nanowire cross bar p-n junction solar cell. This direct printing process will give the single nanowire solar cell the opportunity of the integration on the circuit board with other nanowire functional devices.

• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.144.1-144.1
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• 2016

We fabricate organic single crystal nanowire heterojunction p-n diode poly(3-hexylthiophene)(P3HT) and from Phenyl-C61-butyric acid methyl ester(PCBM) using by liquid-bridge mediated nanotransfer molding(LB-nTM) method. LB-nTM has been reported an one step direct printing method for making well-aligned nanowire arrays. Moreover, multi-patterning nanostructures can be fabricated with the consecutive printing process. As a result, it is possible to make simple and basic concept of heterojunction devices such as lateral organic p-n nanojunction diode. P3HT/PCBM nanowires heterojunction diode has rectifying behavior with on/off ratios of ~20.

• 한국초전도학회:학술대회논문집
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• v.9
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• pp.238-241
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• 1999

Analog-to-digital converter has attracted a lot of interests as one of the most prospective area of an application of Josephson Junction technology. Recently, the development of a digital-to-analog converter has been pursued to achieved the high performance. One of the main advantage in using single flux quantum logic in a digital-to-analog converter is the low voltage drop in a single Josephson Junction and hence the resolution of the output voltage of this digital-to-analog converter can be very high. In this work, we have used a software, called WRspice, to study a voltage multiplier circuit which is the basic block in building a digital-to-analog circuit. In simulation, we operated a voltage multiplier with .4 Josephson Junctions per stage and studied the dependence on the circuit bias currents and the circuit inductors of the voltage multiplier. Our simulation results showed a fast operation and reasonable circuit margins.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.07a
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• pp.206-209
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• 2002

With the progress of semiconductor processing technology, avalanohe photodiodes (APDs) based on InP/InGaAs are used for high-speed optical receiver modules. Planar-type APDs give higher reliability than mesa-type APDs. However, Planar-type APDs are struggled with a problem of intensed electric field at the junction curvature, which causes edge breakdown phenomena at the junction periphery. In this paper, we focused on studying the effects of junction curvature for APDs performances by different etching processes followed by single diffusion to from p-n junction. The performance of each process is characterized by observing electric field profiles and carrier generation rates. From the results, it can be understood to predict the optimum structure, which can minimize edge breakdown and improve the manufacturability.

• ETRI Journal
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• v.37 no.5
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• pp.951-960
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• 2015

For a conventional power metal-oxide-semiconductor field-effect transistor (MOSFET), there is a trade-off between specific on-state resistance and breakdown voltage. To overcome this trade-off, a super-junction trench MOSFET (TMOSFET) structure is suggested; within this structure, the ability to sense the temperature distribution of the TMOSFET is very important since heat is generated in the junction area, thus affecting its reliability. Generally, there are two types of temperature-sensing structures-diode and resistive. In this paper, a diode-type temperature-sensing structure for a TMOSFET is designed for a brushless direct current motor with on-resistance of $96m{\Omega}{\cdot}mm^2$. The temperature distribution for an ultra-low on-resistance power MOSFET has been analyzed for various bonding schemes. The multi-bonding and stripe bonding cases show a maximum temperature that is lower than that for the single-bonding case. It is shown that the metal resistance at the source area is non-negligible and should therefore be considered depending on the application for current driving capability.

• Journal of Korean Foot and Ankle Society
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• v.22 no.1
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• pp.21-25
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• 2018

Purpose: To analyze the correlation between a rupture of the hypovascular zone and early single heel raising after Achilles tendon repair. Materials and Methods: From January 2012 to August 2015, 68 patients, who underwent surgical treatment for a Achilles tendon rupture using Krackow method, were analyzed retrospectively. The patients were divided into two groups according to possibility of single heel raises within 3 months postoperatively. During the periodic outpatient observations, the visual analogue scale, Achilles tendon total rupture score (ATRS), and timing capable single heel raises were evaluated. In addition, the preoperative defect size and distance between the calcaneal osteotendinous junction and the rupture site were measured by ultrasound in all cases. Results: Twenty-three patients could perform a single heel raise within 3 months after surgery (early single heel raise group), and fortyfive patients could perform a single heel raise after 3 month postoperatively. The age, gender, body mass index, smoking, and operation delay were similar in the two groups. In addition, the defect size and distance between the calcaneal osteotendinous junction and rupture site as measured by preoperative ultrasound were similar (p=0.379 and p=0.631, respectively). On the other hand, when the rupture site was divided into the hypovascular zone (4~7 cm from calcaneal osteotendinous junction) and non-hypovascular zone, the hypovascular zone rupture rate was significantly lower in the early single heel raise group (60.9%, 14/23; 91.1%, 41/45; p=0.003). In logistic regression analysis, the odds of the hypovascular zone rupture group being capable of early single heel raise were 0.189 (p=0.017). The ATRS score at 3 months and 1 year after surgery were significantly higher in the early single heel raise group (p<0.001). Conclusion: Achilles tendon rupture at the hypovascular zone is a poor prognostic factor for early single heel raise and might affect the prognosis significantly after an Achilles tendon rupture operation.

• 한국초전도학회:학술대회논문집
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• v.9
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• pp.13-15
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• 1999

A Josephson sampler circuit using high-Tc superconductor (HTS) ramp-edge junctions has been designed, fabricated, and experimentally tested. It consists of five ramp-edge junctions with a stacked groundplane and is based on single-flux-quantum (SFQ) operations. The sampler was used to measure current waveforms at picosecond and microampere resolutions. We are developing a system based on the sampler for measuring the current waveform in a room-temperature sample. And measuring current flowing through wiring in a semiconductor large-scale integrated circuit is a promising application for the HTS sampler system.

• Progress in Superconductivity
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• v.1 no.2
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• pp.81-84
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• 2000

A Josephson sampler circuit using high-Tc superconductor (HTS) ramp-edge junctions has been designed, fabricated, and experimentally tested. It consists of five ramp-edge junctions with a stacked groundplane and is based on single-flux-quantum (SFQ) operations. The sampler was used to measure current waveforms at picosecond and microampere resolutions. We are developing a system based on the sampler for measuring the current waveform in a room-temperature sample. And measuring current flowing through wiring in a semiconductor large-scale integrated circuit is a promising application for the HTS sampler system.

• Proceedings of the Korea Institute of Applied Superconductivity and Cryogenics Conference
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• 2002.02a
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• pp.131-134
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• 2002

In this work, we have developed a systematic way of utilizing the basic design tools for superconductive electronics. This include WRSPICE, XIC, margin program, and L-meter. Since the high performance analog-to- digital converter can be built with Rapid Single Flux Quantum (RSFQ) logic circuits the development of superconductive analog-to-digital converter has attracted a lot of interests as one of the most prospective area of the application of Josephson Junction technology. One of the main advantages in using Rapid Single Flux Quantum logic in the analog-to-digital converter is the low voltage output from the Josephson junction switching, and hence the high resolution. To design an 1-bit analog-digital converter, first we have used XIC tool to compose a circuit schematic, and then studied the operational principle of the circuit with WRSPICE tool. Through this process, we obtained the proper circuit diagram of an 1-bit analog-digital converter circuit. Based on this circuit we performed margin calculations of the designed circuits and optimized circuit parameters. The optimized circuit was laid out as a mask drawing. Inductance values of the circuit layout were calculated with L-meter. Circuit inductors were adjusted according to these calculations and the final layout was obtained.