• Journal of the Speleological Society of Korea
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• no.82
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• pp.5-7
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• 2007

In this paper, p-n junction formation using screen-printed metalization and co-firing is used to fabricate high-efficiency solar cells on single- crystalline silicon substrates. In order to form high-quality contacts, co-firing of a screen-printed Ag grid on the front and Al on the back surface field is implemented. These contacts require low contact resistance, high conductivity, and good adhesion to achieve high efficiency. Before co-firing, a statistically designed experiment is conducted. After the experiment, a neural network (NN) trained by the error back-propagation algorithm is employed to model the crucial relationships between several input factors and solar cell efficiency. The trained NN model is also used to optimize the beltline furnace process through genetic algorithms.

• Proceedings of the KIEE Conference
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• 2004.07e
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• pp.110-113
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• 2004

PV model is presented based on the shockley diode equation. The simple model has a photo-current source, an single diode junction and a series resistance and includes temperature dependences. An accurate PV module electrical model is presented, matching with boost converter MPPT strategy and demosnstarted in Matlab for a typical general purpose solar cell. Given solar insolation and temperature, the model returns current vector and MPP.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.29A no.2
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• pp.55-62
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• 1992

Polycrystalline silicon ingots were manufactured using the casting method for polycrystalline silicon solar cells. These ingots were cut into wafers and ten n$^{+}$p type solar cells were made through the following simple process` surface etching, n$^{+}$p junction formation, metalization and annealing. For the grain boundary passivation, the samples were oxidized in O$_2$ for 5 min. at 80$0^{\circ}C$ prior to diffusion in Ar for 100 min. at 95$0^{\circ}C$. The conversion efficiency of polycrystalline silicon solar cells made from these wafers showed about 70-80% of those of the single crystalline silicon solar cell and superior conversion efficiency, compared to those of commercial polycrystalline wafers of Wacker Chemie. The maximum conversion efficiency of our wafers was indicated about 8%(without AR coating) in spite of such a simple fabrication method.

• Rapid Communication in Photoscience
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• v.4 no.2
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• pp.29-30
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• 2015

Since the first report on long-term durable perovskite solar cell in 2012, a surge of interest in perovskite solar cell has been received due to its superb photovoltaic performance exceeding 20%. $MAPbI_3$ ($MA=CH_3NH_3$) perovskite film is able to be prepared simply by solution processesof either sequential two-step or single step procedure. Since $MAPbI_3$ shows balanced charge transport property with micrometer scale charge diffusion length, it can be applied to any kind of junction structures. Mostly studied structure is mesoscopic structure employing mesoporous oxide layer in perovskite film. Photovoltaic performance is primarilyin fluenced by the quality of perovskite film but interfaces are equally important. In this mini review, emergence and evolution of perovskite solar cell are described.

• 제어로봇시스템학회:학술대회논문집
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• 1995.10a
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• pp.79-82
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• 1995

The problem of temperature control for rapid thermal processing (RTP) in semiconductor manufacturing is discussed in this paper. Among sub=micron technologies for VLSI devices, reducing the junction depth of doped region is of great importance. This paper investigates existing methods for manufacturing wafers, focusing on the RPT which is considered to be good for formation of shallow junctions and performs the wafer fabrication operation in a single chamber of annealing, oxidation, chemical vapor deposition, etc., within a few minutes. In RTP for semiconductor manufacturing, accurate and uniform control of the wafer temperature is essential. In this paper, a robustr controller is designed using a recently developed optimization technique. The controller designed is then tested via computer simulation and compared with the other results.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.283-286
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• 1999

A 2㎓, low noise, low power CMOS voltage-controlled oscillator (VCO) with an integrated LC resonator is presented. The design of VCO relies heavily on the on-chip spiral inductor. An optimized spiral inductor with Q-factor of nearly 8 is achieved and used for the VCO. The simulated result of phase noise is as low as -l14 ㏈c/Hz at an offset frequency of a 600KHz from a 2㎓ carrier frequency. The VCO is tuned with standard available junction capacitors, resulting in an about 400MHz tuning range (20%). Implemented in a five-metal 0.25${\mu}{\textrm}{m}$ standard CMOS process, the VCO consumes only 2㎽ from a single 2.5V supply. It occupies an active area of 620${\mu}{\textrm}{m}$$\times$720${\mu}{\textrm}{m}$.

• Proceedings of the KIEE Conference
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• 2008.10c
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• pp.177-179
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• 2008

This paper, we proposed the theoretical model which includes series resistance $R_s$ and shunt resistance $R_{sh}$ of single-crystalline PV module and used numerical method based on physics. Series resistance $R_s$ was derived from approach for p-n junction diode instead of established form obtained from the simulator with irradiance changes. Electrical output characteristics for PV modules to count the effect of $R_s$ were then studied. Finally simulation results were compared to experimental data leading to good agreement.

• Proceedings of the KACD Conference
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• 2001.11a
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• pp.586.1-586
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• 2001

Large butt-joint box typed class II cavites with cervical margins 1mm below the cemento-enamel junction were cut into 70 extracted human molars. The cavities(7 groups, n=10) were filled using a closed/open sandwich restoration or total bond restoration technique with materials according to the manufacturer's recommandation using the single-component bonding agent for each system. Teeth were thermocycled 500 times between $5^{\circ}C$ and $55^{\circ}C$ with 30-second dwell times.(omitted)

• Progress in Superconductivity
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• v.8 no.2
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• pp.138-142
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• 2007

We observed discrete fluxon-flow resonance steps in high magnetic fields in a stack of Josephson junctions with lateral size of $1.5{\times}17{\mu}m^2$. The measurement sample was prepared by sandwiching a stack of $Bi_2Sr_2CaCu_2O_{8+x}$ intrinsic Josephson junctions between two Au electrodes by using the double-side-cleaving technique. This technique allowed us to isolate the intrinsic Josephson junction structures from the inductive interference of the basal stack. The resonance steps observed are in good agreement with the collective Josephson fluxon dynamics that are in resonance with the plasma oscillation modes inside the stacked Josephson junctions.

• Progress in Superconductivity
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• v.9 no.2
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• pp.157-161
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• 2008

Due to high speed operations and ultra low power consumptions RSFQ logic circuit is a very good candidate for future electronic device. The focus of the RSFQ circuit development has been on the advancement of analog-to-digital converters and microprocessors. Recent works on RSFQ ALU development showed the successful operation of an 1-bit block of ALU at 40 GHz. Recently, the study of an RSFQ analog-to-digital converter has been extended to the development of a single chip RF digital receiver. Compared to the voltage logic circuits, RSFQ circuits operate based on the pulse logic. This naturally leads the circuit structure of RSFQ circuit to be pipelined. Delay time on each pipelined stage determines the ultimate operating speed of the circuit. In simulations, a two junction Josephson transmission line's delay time was about 10 ps, a splitter's 14.5 ps, a switch's 13 ps, a half adder's 67 ps. Optimization of the 4-bit ALU circuit has been made with delay time consideration to operate comfortably at 10 GHz or above.