• Title/Summary/Keyword: Simulation verification

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Dynamic Verification Methodology of User Code in AddSIM Environment (AddSIM 환경에서의 사용자 코드 동적 검증 방법론)

  • Yang, Jiyong;Choi, Changbeom
    • Journal of the Korea Society for Simulation
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    • v.28 no.1
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    • pp.41-47
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    • 2019
  • Defense simulation is actively used to test various weapon systems and evaluate their effectiveness. The AddSIM environment is a simulation framework designed to support the weapon systems dealt with in defense simulation from an integrated point of view and is designed for reuse and scalability. Models used in AddSIM require base model structure fidelity and verification of user code area. Therefore, this paper describes the dynamic verification method used for completeness of models used in AddSIM. For the dynamic verification of user code, the specification method and the verification algorithm are described. Also, we introduce the prototype of the dynamic verifier implemented based on verification specification method and algorithm. The case study analyzes the verification results based on the simulation example implemented in AddSIM environment.

Simulation-based Design Verification for High-performance Computing System

  • Jeong Taikyeong T.
    • Journal of Korea Multimedia Society
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    • v.8 no.12
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    • pp.1605-1612
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    • 2005
  • This paper presents the knowledge and experience we obtained by employing multiprocessor systems as a computer simulation design verification to study high-performance computing system. This paper also describes a case study of symmetric multiprocessors (SMP) kernel on a 32 CPUs CC-NUMA architecture using an actual architecture. A small group of CPUs of CC-NUMA, high-performance computer system, is clustered into a processing node or cluster. By simulating the system design verification tools; we discussed SMP OS kernel on a CC-NUMA multiprocessor architecture performance which is $32\%$ of the total execution time and remote memory access latency is occupied $43\%$ of the OS time. In this paper, we demonstrated our simulation results for multiprocessor, high-performance computing system performance, using simulation-based design verification.

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Solution verification procedures for modeling and simulation of fully coupled porous media: static and dynamic behavior

  • Tasiopoulou, Panagiota;Taiebat, Mahdi;Tafazzoli, Nima;Jeremic, Boris
    • Coupled systems mechanics
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    • v.4 no.1
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    • pp.67-98
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    • 2015
  • Numerical prediction of dynamic behavior of fully coupled saturated porous media is of great importance in many engineering problems. Specifically, static and dynamic response of soils - porous media with pores filled with fluid, such as air, water, etc. - can only be modeled properly using fully coupled approaches. Modeling and simulation of static and dynamic behavior of soils require significant Verification and Validation (V&V) procedures in order to build credibility and increase confidence in numerical results. By definition, Verification is essentially a mathematics issue and it provides evidence that the model is solved correctly, while Validation, being a physics issue, provides evidence that the right model is solved. This paper focuses on Verification procedure for fully coupled modeling and simulation of porous media. Therefore, a complete Solution Verification suite has been developed consisting of analytical solutions for both static and dynamic problems of porous media, in time domain. Verification for fully coupled modeling and simulation of porous media has been performed through comparison of the numerical solutions with the analytical ones. Modeling and simulation is based on the so called, u-p-U formulation. Of particular interest are numerical dispersion effects which determine the level of numerical accuracy. These effects are investigated in detail, in an effort to suggest a compromise between numerical error and computational cost.

End-mill Manufacturing and Developing of Processing Verification via Cutting Simulation (Cutting Simulation을 이용한 End-milling Cutter의 제작 및 가공 검증 기술 개발)

  • Kim J.H.;Kim J.H.;Ko T.J.;Park J.W.;Kim H.S.
    • Proceedings of the Korean Society of Precision Engineering Conference
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    • 2006.05a
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    • pp.453-454
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    • 2006
  • This paper describes a processing verification technique for developing about end-milling cutters. Developed software is processing verification module for manufacturing. By using cutting simulation method, we can obtain center points of finding wheel via Boolean operation between a grinding wheel and a cylindrical workpiece. The obtained CL data can be used for calculating NC data. After then, we can simulate by using designed grinding machine and NC data. This research has been implemented on a commercial CAD system by using the API function programming. The operator can evaluate the cutting simulation process and reduce the time of design and manufacturing.

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Design of a Vehicle Assembly Line Using PLC Simulation (PLC 시뮬레이션을 이용한 자동차 조립 라인 설계)

  • Lee, Chang-Ho;Wang, Gi-Nam;Park, Sang-Chul
    • Korean Journal of Computational Design and Engineering
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    • v.14 no.5
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    • pp.323-329
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    • 2009
  • Auto-makers can only remain competitive by producing high quality vehicles in an efficient way. In designing a production line, one of the most important objectives of digital manufacturing is to verify design errors as early as possible. In terms of the cost and time saving, it is very essential to start the construction of a production line with a proven design which is error-free. Likewise, this paper aims to implement PLC verification using an example. The verification in automobile manufacturing means verifying PLC program, which control automatic devices. In this paper, we built a virtual factory to implement PLC simulation and introduced verification procedure using PLC Studio. Finally, we can prove the availability for the PLC verification.

Method and Implementation (or Consistency Verification of DEVS Model against User Requirement (DEVS 모델과 사용자 요구사항의 일관성 검증 방법론 및 환경 구현)

  • Kim Do-Hyung;Kim Tag-Gon
    • Proceedings of the Korea Society for Simulation Conference
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    • 2005.05a
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    • pp.100-105
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    • 2005
  • Development of complex discrete event simulators requires cooperation between domain experts and modeling experts who involve the development. With the cooperation the domain experts derive user requirement and modeling experts transform the requirement to a simulation model. This paper proposes a method for consistency verification of simulation model in DEVS formalism against the user requirement in UML diagrams. It also presents an automated tool, called VeriDEVS, which implements the proposed method. Inputs of VeriDEVS are three UML diagrams, namely use case, class and sequence diagrams, and DEVS Graph, all in Visio; outputs of a verification result is represented in PowerPoint files.

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A Traffic Simulation Model Verification Method Using GPS Equipment (GPS를 활용한 교통 시뮬레이션 모형 검증)

  • Hu, Hyejung;Baek, Jongdae;Han, Sangjin
    • The Journal of The Korea Institute of Intelligent Transport Systems
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    • v.11 no.5
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    • pp.62-69
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    • 2012
  • Traffic simulation models have been used for assessing various transportation strategies. Through comparing results from a simulation model and real field data, researchers try to show how close the model can reproduce the real world traffic. This model verification step is one of the most essential tasks in modeling procedure. Traffic counts and speeds have been frequently used for the verification or validation. Authors modeled severe PM peak bottleneck situation on the I-40 corridor in Raleigh, North Carolina using DYNASMART-P, a mesoscopic traffic simulation tool and verified the model. NCDOT has Traffic Information Management System which has archive capability for the traffic speeds on the I-40 corridor. However, the authors selected travel time as the field measure for model verification and collected the data using a GPS equipment because the speed data from NCDOT speed detectors are spot speeds which are not appropriate for comparison with link average speed from the simulation model. This paper describes the GPS field data collection procedure, the model verification method, and the results.

Efficient Simulation Acceleration by FPGA Compilation Avoidance (FPGA 컴파일 회피에 의한 효과적인 시뮬레이션 가속)

  • Shim, Kyu-Ho;Park, Chang-Ho;Yang, Sei-Yang
    • The KIPS Transactions:PartA
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    • v.14A no.3 s.107
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    • pp.141-146
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    • 2007
  • In this paper, we proposed an efficient FPGA-based simulation acceleration method based on FPGA compilation avoidance, which can effectively decrease the long debugging turnaround time incurred from the every debugging process in the functional verification. The proposed method had been experimentally applied to the functional verification for a microcontroller design. It had clearly shown that the debugging turnaround time was greatly reduced while the high simulation speed of the simulation acceleration was still maintained.

Verification of Tool Collision for 3-Axis Milling (3축 밀링 가공의 공구 충돌 검증)

  • Chung, Yun-Chan;Park, Jung-Whan
    • Journal of the Korean Society for Precision Engineering
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    • v.19 no.6
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    • pp.35-42
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    • 2002
  • Verification of tool collision Is an important issue in die and mold machining. In this paper three functions of verification for 3-axis milling machining are schematically explained. Operators of geometric models are explained at first, which will be used in the functions of verification. The first verification function is getting a collision-free region when a tool assembly and a part surface model are given. The second function estimates the shortest length of cutter shank with that the tool cuts all of a region without collision The last one is cutting simulation considering all parts of tool assembly as well as cutter blade. Proposed approaches can be easily implemented by using several basic operators of geometric model. An example to calculate collision-free region is presented also.

Virtual Environment Hardware-In-the-Loop Simulation for Verification of OHT Controller (OHT 제어기 검증을 위한 가상환경 HIL 시뮬레이션)

  • Lee, Kwan Woo;Lee, Woong Geun;Park, Sang Chul
    • Journal of the Korea Society for Simulation
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    • v.28 no.4
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    • pp.11-20
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    • 2019
  • This paper presents a HILS(Hardware-In-the-Loop Simulation) approach for the verification of the OHT (Overhead Hoist Transport) controller in a semiconductor FAB. Since hundreds of OHTs can run simultaneously on the OHT network of a FAB, the full verification of the OHT controller is very essential to guarantee the stableness of the material handling system. The controller needs to fully consider not only normal situations but also abnormal situations that are difficult to predict. For the verification of the controller, we propose a HILS approach using a virtual environment including OHTs on a rail network, which can generate abnormal situations. The proposed HILS approach has been implemented and tested with various examples.