• The Journal of the Acoustical Society of Korea
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• v.6 no.3
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• pp.52-59
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• 1987

In this paper, we present a method of realizing an infinite impulse response (IIR) digital filter (DF)using linear delta modulation (LDM) as a simple analog/digital (A/D) converter. This method makes the realization of IIR digital filters much simpler than that of conventional ones because it does not require hardware multipliers and a pulse code modulation (PCM) A/D converter. Compared to the finite impulse respponse (FIR) LDMDF of Lee and Un [1] , this IIR LDMDF requires significantly less computation time.

• Proceedings of the KIEE Conference
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• 1988.07a
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• pp.282-284
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• 1988

In this paper, a method for constructing parallel-in, parallel-out multipliers in GF($2^{m}$) is presented. The proposed system is composed of two operational parts by using shift register. One is a multiplicative arithmetical operation part capable of the multiplicative arithmetic and modulo 2 operation to all product terms with the same degree. And the other is an irreducible polynomial operation part to outputs from the multiplicative arithmetical operation part. Since the total hardware is linearly m dependant to an GF($2^{m}$), this system has a reasonable merit when m increases. And also this system is suited for VLSI implementation due to simple, regular, and concurrent properties.

• Proceedings of the IEEK Conference
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• 2000.07b
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• pp.1029-1032
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• 2000

A neuro-fuzzy based circuit to recognize circuit pat-terns is proposed in this paper. The simple algorithm and exemption from the use of template patterns as well as multipliers enable the proposed circuit to implement on the hardware of an economical scale. Furthermore, thanks to the circuit design by using current-mode techniques, the proposed circuit call achieve easy extendability of tile circuit and efficient pattern recognition with high-speed. The validity of the proposed algorithm and tile circuit design is confirmed by computer simulations. The proposed pattern recognition circuit is integrable by a standard CMOS technology.

• Proceedings of the KIEE Conference
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• 1999.07g
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• pp.3187-3189
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• 1999

A novel wide-tunable quadratic gamma corrector for HDTV camera applications is proposed. The new gamma corrector controls gamma value in a wide range by simple electrical adjustment of multipliers' gain. It has wide signal bandwidth of 30MHz sufficient for HDTV applications. It also simplifies the circuit design, resulting in a compact surface mounting board implementation with reduced power consumption. Simulation and experimental results confirm these characteristics.

• Journal of the Institute of Convergence Signal Processing
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• v.2 no.3
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• pp.102-109
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• 2001

In this paper, a new multiplication algorithm which describes the methods of constructing a multiplierover GF(p$^{m}$ ) was presented. For the multiplication of two elements in the finite field, the multiplication formula was derived. Multiplier structures which can be constructed by this formula were considered as well. For example, both GF(3) multiplication module and GF(3) addition module were realized by current-mode CMOS technology. By using these operation modules the basic cell used in GF(3$^{m}$ ) multiplier was realized and verified by SPICE simulation tool. Proposed multipliers consisted of regular interconnection of simple cells use regular cellular arrays. So they are simply expansible for the multiplication of two elements in the finite field increasing the degree m.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.9
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• pp.2121-2126
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• 2013

This paper compares radix-2 based structures for 32768-point FFT. Radix-$2^k$ structures have been widely used because the butterfly is simple and the number of multipliers can be reduced in those structures. This paper applied various radix-$2^k$ structures to 32768-point FFT that is representing ultra-long FFT. The ultra-long FFT has been studied much recently. This paper shows that the radix-$2^4$ structure is the most adequate because it shows the smallest complexity in the synthesis and the best SQNR performance. should be placed here.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.1
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• pp.37-42
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• 2008

In this paper, we propose a partial product addition method using variable groups in the design of operators such as multipliers and digital filters. By this method, full adders can be replaced with simple logic circuits. To show the efficiency of the proposed method, we applied the method to the design of squarers and precomputer blocks of FIR filters. In case of 7 bit and 8 bit squarers, it is shown that by the proposed method, area, power and delay time can be reduced up to {22.1%, 20.1%, 14%} and {24.7%, 24.4%, 6.7%}, respectively, compared with the conventional method. The proposed FIR precomputer circuit leads to up to {63.6%, 34.4%, 9.8%} reduction in area, power consumption and propagation delay compared with previous method.

• Journal of IKEEE
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• v.25 no.4
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• pp.697-702
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• 2021

Fast Fourier Transform (FFT) is a major signal processing block being widely used. For long-point FFT processing, usually more than 1024 points, its low-complexity implementation becomes very important while retaining high SQNR (Signal-to-Quantization Noise Ratio). In this paper, we present a low-complexity FFT algorithm with a simple dynamic scaling scheme. For the 2048-point pipelined FFT processing, we can reduce the number of general multipliers by half compared to the well-known radix-2 algorithm. Also, the table size for twiddle factors is reduced to 35% and 53% compared to the radix-2 and radix-2² algorithms respectively, while achieving SQNR of more than 55dB without increasing the internal wordlength progressively.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.6
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• pp.22-34
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• 2010

Existing image scalers generally adopt simple interpolation methods such as bilinear method to take cost-benefit, or highly complex architectures to achieve high quality resulting images. However, demands for a low power, low cost, and high performance image scaler become more important because of emerging high quality mobile contents. In this paper we propose the novel low power hardware architecture for a high quality raster scan image scaler. The proposed scaler architecture enhances the existing cubic interpolation look-up table architecture by reducing and optimizing memory access and hardware components. The input data buffer of existing image scaler is replaced with line memories to reduce the number of memory access that is critical to power consumption. The cubic interpolation formula used in existing look-up table architecture is also rearranged to reduce the number of the multipliers and look-up table size. Finally we analyze the optimized parameter sets of look-up table, which is a trade-off between quality of result image and hardware size.

• Journal of Biomedical Engineering Research
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• v.24 no.2
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• pp.83-89
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• 2003

The gas electron multiplier placed in the drift volume of conventional gas detectors, is a conceptually simple device for producing a large gas gain by concentrating the drift electric field over a very short distance to the point that electron avalanching occurs(〉 10$^4$ V/cm), greatly increasing the number of drifting electrons. This device consists of a thin insulating foil of several tens of urn in thickness. covered on each side with a thin metal layer(Cu), with tiny holes, usually 100 ${\mu}{\textrm}{m}$ or less in diameter. and with a spacing of 100-200 ${\mu}{\textrm}{m}$ through the entire foil. perforated by using chemical etching or high-powered laser beam technique In this study, we have investigated its operating properties with various experimental conditions, and demonstrated the possibility of using this device as a digital X-ray imaging sensor, by acquiring X-ray images based on the scintillation properties of the gas electron multiplier with standard CCD camera.