• 제목/요약/키워드: Silicon-on-Insulator technology

검색결과 106건 처리시간 0.029초

폴리카보실란을 이용하여 탄소단열재에 코팅한 실리콘카바이드 코팅막의 내산화 특성 (Preperation of Silicon Carbide Oxidation Protection Film on Carbon Thermal Insulator Using Polycarbosilane and Its Characterization)

  • 안수빈;이윤주;방정원;신동근;권우택
    • 한국재료학회지
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    • 제27권9호
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    • pp.471-476
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    • 2017
  • In order to improve the high temperature oxidation resistance and lifespan of mat type porous carbon insulation, SiC was coated on carbon insulation by solution coating using polycarbosilane solution, curing in an oxidizing atmosphere at $200^{\circ}C$, and pyrolysis at temperatures up to $1200^{\circ}C$. The SiOC phase formed during the pyrolysis process was converted into SiC crystals as the heat treatment temperature increased, and a SiC coating with a thickness of 10-15 nm was formed at $1600^{\circ}C$. The SiC coated specimen showed a weight reduction of 8.6 % when it was kept in an atmospheric environment of $700^{\circ}C$ for 1 hour. On the other hand, the thermal conductivity was 0.17 W/mK, and no difference between states before and after coating was observed at all.

Optimizing Effective Channel Length to Minimize Short Channel Effects in Sub-50 nm Single/Double Gate SOI MOSFETs

  • Sharma, Sudhansh;Kumar, Pawan
    • JSTS:Journal of Semiconductor Technology and Science
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    • 제8권2호
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    • pp.170-177
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    • 2008
  • In the present work a methodology to minimize short channel effects (SCEs) by modulating the effective channel length is proposed to design 25 nm single and double gate-source/drain underlap MOSFETs. The analysis is based on the evaluation of the ratio of effective channel length to natural/ characteristic length. Our results show that for this ratio to be greater than 2, steeper source/drain doping gradients along with wider source/drain roll-off widths will be required for both devices. In order to enhance short channel immunity, the ratio of source/drain roll-off width to lateral straggle should be greater than 2 for a wide range of source/drain doping gradients.

벌크 FinFET의 기술 동향 및 이슈 (Trend and issues of the bulk FinFET)

  • 이종호;최규봉
    • 진공이야기
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    • 제3권1호
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    • pp.16-21
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    • 2016
  • FinFETs are able to be scaled down to 22 nm and beyond while suppressing effectively short channel effect, and have superior performance compared to 2-dimensional (2-D) MOSFETs. Bulk FinFETs are built on bulk Si wafers which have less defect density and lower cost than SOI(Silicon-On-Insulator) wafers. In contrast to SOI FinFETs, bulk FinFETs have no floating body effect and better heat transfer rate to the substrate while keeping nearly the same scalability. The bulk FinFET has been developed at 14 nm technology node, and applied in mass production of AP and CPU since 2015. In the development of the bulk FinFETs at 10 nm and beyond, self-heating effects (SHE) is becoming important. Accurate control of device geometry and threshold voltage between devices is also important. The random telegraph noise (RTN) would be problematic in scaled FinFET which has narrow fin width and small fin height.

Theoretical and Experimental Analysis of Back-Gated SOI MOSFETs and Back-Floating NVRAMs

  • Avci, Uygar;Kumar, Arvind;Tiwari, Sandip
    • JSTS:Journal of Semiconductor Technology and Science
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    • 제4권1호
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    • pp.18-26
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    • 2004
  • Back-gated silicon-on-insulator MOSFET -a threshold-voltage adjustable device-employs a constant back-gate potential to terminate source-drain electric fields and to provide carrier confinement in the channel. This suppresses shortchannel effects of nano-scale and of high drain biases, while allowing a means to threshold voltage control. We report here a theoretical analysis of this geometry to identify its natural length scales, and correlate the theoretical results with experimental device measurements. We also analyze experimental electrical characteristics for misaligned back-gate geometries to evaluate the influence on transport behavior from the device electrostatics due to the structure and position of the back-gate. The backgate structure also operates as a floating-gate nonvolatile memory (NVRAM) when the back-gate is floating. We summarize experimental and theoretical results that show the nano-scale scaling advantages of this structure over the traditional front floating-gate NVRAM.

SOI 슬롯 광 도파로 기반 단일 및 삽입-분기 채널 링-공진형 바이오·케미컬 집적광학 센서의 제원에 대한 감도 해석 (Sensitivity Analysis for Specifications of Silicon-on-Insulator (SOI) Slot Optical Waveguide-based Single and Add-drop Channel Ring-resonant Biochemical Integrated Optical Sensors)

  • 장재식;정홍식
    • 센서학회지
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    • 제31권2호
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    • pp.107-114
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    • 2022
  • The effects of ring radius and coupling spacing on the free spectral range (FSR), full width at half maximum (FWHM), quality factor, and sensitivity of single-channel and add-drop channel slot ring resonators were systematically investigated using FIMMPROP and PICWAVE numerical software. The single-channel ring resonator exhibited better characteristics, namely, a wider FSR and narrower FWHM compared with the add-drop structure; thus, it was evaluated to be more suitable for biochemical sensors. The FSR, FWHM, quality factor, and sensitivity for a single channel ring resonator with a radius of 59.4 ㎛ and coupling gap of 0.5 ㎛ were 2.4 nm, 0.087 nm, 17677, and 550 [nm/RIU], respectively.

Midinfrared Refractive-index Sensor with High Sensitivity Based on an Optimized Photonic Crystal Coupled-cavity Waveguide

  • Han, Shengkang;Wu, Hong;Zhang, Hua;Yang, Zhihong
    • Current Optics and Photonics
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    • 제5권4호
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    • pp.444-449
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    • 2021
  • A photonic crystal coupled-cavity waveguide created on silicon-on-insulator is designed to act as a refractive-index-sensing device at midinfrared wavelengths around 4 ㎛. To realize high sensitivity, effort is made to engineer the structural parameters to obtain strong modal confinement, which can enhance the interaction between the resonance modes and the analyzed sample. By adjusting some parameters, including the shape of the cavity, the width of the coupling cavity, and the size of the surrounding dielectric columns, a high-sensitivity refractive-index sensor based on the optimized photonic crystal coupled-cavity waveguide is proposed, and a sensitivity of approximately 2620 nm/RIU obtained. When an analyte is measured in the range of 1.0-1.4, the sensor can always maintain a high sensitivity of greater than 2400 nm/RIU. This work demonstrates the viability of high-sensitivity photonic crystal waveguide devices in the midinfrared band.

고해상도의 Foxtail형 정전력 마이크로구동기에 대한 연구 (A Study on a Foxtail Electrostatic Microactuator with a High Resolution)

  • 김만근;김영윤;조경우;이종현
    • 한국정밀공학회:학술대회논문집
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    • 한국정밀공학회 2005년도 춘계학술대회 논문집
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    • pp.1198-1201
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    • 2005
  • A new foxtail actuator driven by V-shape beam deflection using electrostatic force has been designed, fabricated and characterized for nano-resolution manipulators. The proposed foxtail mechanism was implemented using a pair of electrostatic actuators and a pair of holding actuators, which was analyzed based on the electromechanically coupled motion of voltage - displacement relation. The proposed actuator was fabricated onto Silicon-on-Insulator (SOI) wafer and its stepping characteristics were measured by micro optical interferometer consisting of integrated micromirror and optical fiber. The fabricated foxtail microactuator was successfully operated from 1nm to 76nm, and the magnitude of step displacement was controllable up from 26nm/cycles to 53nm/cycle by changing the voltage.

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유중 용존수소 감지를 위한 Pd/Pt Gate MISFET 센서의 제조와 그 특성 (Fabrication and Characteristics of Pd/Pt Gate MISFET Sensor for Dissolved Hydrogen in Oil)

  • 백태성;이재곤;최시영
    • 센서학회지
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    • 제5권4호
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    • pp.41-46
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    • 1996
  • 변압기 절연유중 용존수소를 감지하기 위해 Pd/Pt 게이트 MISFET 센서를 제조하고 그 특성을 조사하였다. 동일 칩안에 내장형 히터와 온도측정용 다이오드를 제조하고 MISFET의 전압 드리프트를 줄이기 위해 차동형구조로 하였다. 수소유입 드리프트를 줄이기 위해, 양쪽 FET의 게이트 절연층을 실리콘 산화막과 실리콘 질화막의 2중 구조로 하였다. 수소감지막의 블리스터를 줄이기 위해 Pd/Pt 2중 금속층을 증착하였다. 제조된 센서의 변압기 절연유에 대한 수소감지 특성은 40mV/10ppm 감도와 0.14mV/day 안정도를 보였다.

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2.2 inch qqVGA AMOLED drived by ultra low temperature poly silicon (ULTPS) TFT direct fabricated below $200^{\circ}C$

  • Kwon, Jang-Yeon;Jung, Ji-Sim;Park, Kyung-Bae;Kim, Jong-Man;Lim, Hyuck;Lee, Sang-Yoon;Kim, Jong-Min;Noguchi, Takashi;Hur, Ji-Ho;Jang, Jin
    • 한국정보디스플레이학회:학술대회논문집
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    • 한국정보디스플레이학회 2006년도 6th International Meeting on Information Display
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    • pp.309-313
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    • 2006
  • We demonstrated 2.2inch qqVGA AMOLED display drived by ultra low temperature poly-Si (ULTPS) TFT not transferred but direct fabricated below $200^{\circ}C$. Si channel was crystallized by decreasing impurity concentration even at room temperature. Gate insulator with a breakdown field exceeding 8 MV/cm was realized by Inductively coupled plasma - CVD. In order to reduce stress of plastic, organic film was coated as inter-dielectric and passivation layers. Finally, ULTPS TFT of which mobility is over $20cm^2/Vsec$ was fabricated on transparent plastic substrate and drived OLED display successfully.

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부분 공핍형 SOI 게이트의 통계적 타이밍 분석 (Statistical Timing Analysis of Partially-Depleted SOI Gates)

  • 김경기
    • 대한전자공학회논문지SD
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    • 제44권12호
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    • pp.31-36
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    • 2007
  • 본 논문은 100 nm BSIMSOI 3.2 기술을 사용한 부분 공핍형 SOI (Partially-Depleted SOI: PD-SOI) 회로들의 정확한 타이밍 분석을 위한 새로운 통계적 특징화 방법과 추정 방법을 제안한다. 제안된 타이밍 추정 방법은 Matlab, Hspice, 그리고 C 언어로 구현되고, ISCAS 85 벤치마크 회로들을 사용해서 검증된다. 실험 편과는 Monte Carlo 시뮬레이션과 비교해 5 % 내의 에러를 보여준다.