• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2001년도 하계학술대회 논문집
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• pp.874-877
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• 2001

SOI(Silicon-On-Insulator) technology is proposed as an alternative to bulk silicon for MEMS(Micro Electro Mechanical System) manufacturing. In this paper, we fabricated the SOI wafer with uniform active layer thickness by silicon direct bonding and mechanical polishing processes. Specially-designed electrostatic bonding system is introduced which is available for vacuum packaging and silicon-glass wafer bonding for SOG(Silicon On Glass) wafer. We demonstrated thermopile sensor and RF resonator using the SOI wafer, which has the merits of simple process and uniform membrane fabrication.

• 정보학연구
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• 제8권2호
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• pp.85-91
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• 2005

We studied a pollution mechanism for simulation of contamination environment in industrial concentrated area of around a metropolitan that made to circulated flow in the chamber. In case of the virgin both side of EPDM or Silicon insulator, we confirmed that the pollution to much more than service insulator in the field. Also contamination of initial state of the virgin didn't falling in spite of physical outside factor easily. This study confirmed to that the silicon was too much accumulated pollution contrast to EPDM insulator from scatter(spray) point to regular interval position use the Kaolin contaminant in the chamber. There are effected to the hydrophobicity of polymer insulator due to the pollution. In ceramic insulator, we get to know that pollution is much more at the Post insulator with vertical than with horizontal setup insulator.

• 동력기계공학회지
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• 제5권4호
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• pp.11-17
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• 2001

Micronization of sensor is a trend of the silicon sensor development with regard to a piezoresistive silicon pressure sensor, the size of the pressure sensor diaphragm have become smaller year by year, and a microaccelerometer with a size less than $200{\sim}300{\mu}m$ has been realized, In this paper, we study some of the bonding processes of SCS(single crystal silicon) insulator wafer for the microaccelerometer. and their subsequent processes which might affect thermal loads. The finite element method(FEM) has been a standard numerical modeling technique extensively utilized in micro structural engineering discipline for design of SCS insulator wafers. Successful temperature distribution analysis and design of the SCS insulator wafers based on the tunneling current concept using microaccelerometer depend on the knowledge about normal mechanical properties of the SCS and $SiO_2$ layer and their control through manufacturing processes.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2007년도 하계학술대회 논문집 Vol.8
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• pp.21-21
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• 2007

Strained silicon 기술은 MOSFET 채널 내 캐리어 이동도를 향상시켜 집적회로의 성능을 향상시키는 기술이다. 최근에는 strained 실리콘 기술과 SOI(silicon On Insulator) 기술을 접목시켜 집적회로 소자의 특성을 더욱 향상시킨 SSOI(Strained Silicon On Insulator) 기술이 연구되고 있다. 본 연구에서는 pseudo MOSFET 측정법을 이용하여 strained SOI 웨이퍼의 전기적 특성 분석을 행하였다. pseudo MOSFET 측정법은 SOI 웨이퍼의 전기적 특성분석을 위해 고안된 방법으로써 산화, 도핑 등의 소자 제조 공정 없이도 SOI 표면 실리콘층의 이동도와 매몰산화막과의 계면 특성 등을 분석해 낼 수 있는 기술이다. 표면 실리콘층의 두께와 매몰산화막의 두께가 각각 60nm, 150nm인 SOI 웨이퍼와 동일한 막 두께를 가지며 표면 실리콘층이 strained silicon인 SSOI 웨이퍼를 제작하여 그 특성을 비교 분석하였다. Pseudo MOSFET 측정 결과 Strained SOI 웨이퍼에서 표면 실리콘총 내의 전자 이동도가 일반적인 SOI 웨이퍼보다 약 25% 향상되었으며 정공 이동도나 매몰산화막의 계면 트랩밀도는 큰 차이를 보이지 않았다.

• 한국광학회:학술대회논문집
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• 한국광학회 2000년도 하계학술발표회
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• pp.156-157
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• 2000

낮은 도핑의 silicon은 광통신에서 사용하는 1.3 및 1.55 um의 광파장 영역에서 0.01dB/cm 이하의 낮은 흡수 손실을 가짐으로 인해, core 층으로 silicon을 사용하며 상부 및 하부 cladding 층으로 SiO$_2$와 같은 유전체 박막 구조를 갖는 SOI (Silicon on Insulator)를 사용한 수동광소자에 대한 연구가 1990년대부터 진행되고 있다. 또한 silicon의 특성상 SOI는strain에 의한 영향이 낮고, 광학적 비등방성이 적어서 polymer 및 silica를 이용한 광소자에 비해 편광의존도가 낮은 광소자를 구현할 수 있는 장점이 있다. 현재까지 연구되어온 SOI 수동광소자의 연구결과는 TE/TM 편광차에 따른 채널분리도가 약 0.04nm, 누화특성이 23dB 인 8채널 AWG의 연구결과가 있었으며, 스위칭시간 < 1msec, 소광비 17 dB의 광결합기와 마하젠더가 혼합된 광변조기 및 Bookham사에서 개발한 RX/TX 양방향 송수신 광모듈에 적용된 1.3/l.55 um 파장선택적 분리기, Silicon-CMOS 증폭기와 집적화된 4channel 광다중 수신기등에 대한 연구결과가 있었다. (중략)

• 대한전기학회논문지
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• 제43권6호
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• pp.1036-1038
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• 1994

In this paper, a silicon piezoresistive accelerometer is designed and fabricated using a silicon direct bonded wafer. The accelerometer consists of a seismic mass and four cantilevers, and is fabricated mainly by the anisotropic etching method using EPW as an etchant. The measured sensitivity and the resonant frequency are 0.02 mV/V.g and 3.4 kHz, respectively. The nonlinearity is less than $\pm$0.3% of the full scale of the output.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2009년도 하계학술대회 논문집
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• pp.95-96
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• 2009

A fully depleted capacitorless 1-transistor dynamic random access memory (FD 1T-DRAM) based on a sSOI strained-silicon-on-insulator) wafer was investigated. The fabricated device showed excellent electrical characteristics of transistor such as low leakage current, low subthreshold swing, large on/off current ratio, and high electron mobility. The FD sSOI 1T-DRAM can be operated as memory device by the floating body effect when the substrate bias of -15 V is applied, and the FD sSOI 1T-DRAM showed large sensing margin and several milli seconds data retention time.

• JSTS:Journal of Semiconductor Technology and Science
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• 제8권3호
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• pp.264-275
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• 2008

Electron mobility has been investigated theoretically in undoped double-gate (DG) MOSFETs of different channel architectures: a relaxed-Si DG SOI, a strained-Si (sSi) DG SSOI (strained-Si-on-insulator, containing no SiGe layer), and a strained-Si DG SGOI (strained-Si-on-SiGe-on-insulator, containing a SiGe layer) at 300K. Electron mobility in the DG SSOI device exhibits high enhancement relative to the DG SOI. In the DG SGOI devices the mobility is strongly suppressed by the confinement of electrons in much narrower strained-Si layers, as well as by the alloy scattering within the SiGe layer. As a consequence, in the DG SGOI devices with thinnest strained-Si layers the electron mobility may drop below the level of the relaxed DG SOI and the mobility enhancement expected from the strained-Si devices may be lost.

• JSTS:Journal of Semiconductor Technology and Science
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• 제3권3호
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• pp.153-166
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• 2003

Failure analysis is fundamental to the design and development methodology of electrostatic discharge (ESD) devices and ESD robust circuits. The role of failure analysis (FA) in the models, methodology, band mechanisms evaluation for improving ESD robustness of semiconductor products in CMOS, silicon-on-insulator (SOI) and silicon germanium (SiGe) technologies will be reviewed.

• 한국컴퓨터산업교육학회:학술대회논문집
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• 한국컴퓨터산업교육학회 2003년도 제4회 종합학술대회 논문집
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• pp.79-82
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• 2003

The electrothermal simulation of high voltage LIGBT(Lateral Insulated Gate Bipolar Transistor) in thin Silicon on insulator (SOI) and Silicon on sapphire (SOS) for thermal conductivity and sink is performed by means of MEDICI. The finite element simulations demonstrate that the thermal conductivity of the buried oxide is an important parameter for the modeling of the thermal behavior of silicon-on-insulator (SOI) devices. In this paper, using for SOI LIGBT, we simulated electrothermal for device that insulator layer with $SiO_2$ and $Al_2O_3$ at before and after latch up to measured the thermal conductivity and temperature distribution of whole device and verified that SOI LIGBT with $Al_2O_3$ insulator had good thermal conductivity and reliability.