• Journal of Power System Engineering
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• v.5 no.4
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• pp.11-17
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• 2001

Micronization of sensor is a trend of the silicon sensor development with regard to a piezoresistive silicon pressure sensor, the size of the pressure sensor diaphragm have become smaller year by year, and a microaccelerometer with a size less than $200{\sim}300{\mu}m$ has been realized, In this paper, we study some of the bonding processes of SCS(single crystal silicon) insulator wafer for the microaccelerometer. and their subsequent processes which might affect thermal loads. The finite element method(FEM) has been a standard numerical modeling technique extensively utilized in micro structural engineering discipline for design of SCS insulator wafers. Successful temperature distribution analysis and design of the SCS insulator wafers based on the tunneling current concept using microaccelerometer depend on the knowledge about normal mechanical properties of the SCS and $SiO_2$ layer and their control through manufacturing processes.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.07a
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• pp.176-180
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• 2003

Tri-crystalline silicon (Tri-Si) wafers have three different orientations and three grain boundaries. In this paper, tri-Si wafers have been used for the fabrication of buried contact solar cells. The optical and micro-structural properties of these cells after texturing in KOH solution have been investigated and compared with those of cast multi-crystalline silicon (multi-Si) wafers. We employed a cost effective fabrication process and achieved buried contact solar cell (BCSC) energy conversion efficiencies up to 15% whereas the cast multi-Si wafer has efficiency around 14%.

• Journal of the Semiconductor & Display Technology
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• v.9 no.2
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• pp.21-25
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• 2010

In response to the industrial needs for automated handling of very thin solar cell wafers, this paper presents the design concept for the individual wafer separation from the stacked wafers by utilizing continuous water jet. The experimental apparatus for automated wafer separation was constructed and it includes the water jet system and the microprocessor controlled wafer stack advancing system. Through a series of tests, the performance of the proposed design is quantified into the success rate of single wafer separation and the rapidity of processing wafer stack. Also, the inclination angle of wafer equipped cartridge and the water jet flowrate are found to be important parameters to be considered for process optimization. The proposed design shows the concept for fast and efficient processing of wafer separation and can be implemented in the automated manufacturing of silicon based solar cell wafers.

• Korean Journal of Materials Research
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• v.20 no.12
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• pp.649-653
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• 2010

In this paper, double texturization of multi crystalline silicon solar cells was studied with laser and reactive ion etching (RIE). In the case of multi crystalline silicon wafers, chemical etching has problems in producing a uniform surface texture. Thus various etching methods such as laser and dry texturization have been studied for multi crystalline silicon wafers. In this study, laser texturization with an Nd:$YVO_4$ green laser was performed first to get the proper hole spacing and $300{\mu}m$ was found to be the most proper value. Laser texturization on crystalline silicon wafers was followed by damage removal in acid solution and RIE to achieve double texturization. This study showed that double texturization on multi crystalline silicon wafers with laser firing and RIE resulted in lower reflectance, higher quantum yield and better efficiency than that process without RIE. However, RIE formed sharp structures on the silicon wafer surfaces, which resulted in 0.8% decrease of fill factor at solar cell characterization. While chemical etching makes it difficult to obtain a uniform surface texture for multi crystalline silicon solar cells, the process of double texturization with laser and RIE yields a uniform surface structure, diminished reflectance, and improved efficiency. This finding lays the foundation for the study of low-cost, high efficiency multi crystalline silicon solar cells.

• Proceedings of the Korean Society of Marine Engineers Conference
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• 2000.05a
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• pp.105-109
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• 2000

Micronization of sensor is a trend of the silicon sensor development with regard to a piezoresistive silicon pressure sensor the size of the pressure sensor diaphragm have become smaller year by year and a microaccelerometer with a size less than 200-300${\mu}m$ has been realized. In this paper we study some of the micromachining processes of SOI(silicon on insulator)for the microaccelerometer and their subsequent processes which might affect thermal loads. The finite element method(FEM) has been a standard numerical modeling technique extensively utilized in structural engineering discipline for design of SOI wafers. Successful thermal behaviors analysis and design of the SOI wafers based on the tunneling current concept using SOI wafer depend on the knowledge abut normal mechanical properties of the SCS(single crystal silicon)layer and their control through manufacturing process

• Journal of the Semiconductor & Display Technology
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• v.13 no.1
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• pp.13-17
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• 2014

Since the semiconductor manufacturing requires the silicon wafers with extraordinary degree of surface flatness, the surface polishing of wafers from ingot cutting is an important process for deciding surface quality of wafers. The present study introduces the development of wafer polishing equipment and, especially, the wafer polishing head that employs the forced self-driving of installed silicon wafer as well as the wax wafer mounting technique. A series of wafer polishing tests have been carried out to investigate the effects of self-driving function in wafer polishing head. The test results for wafer planarization showed that the LLS counts and SBIR of polished wafer surfaces were generally improved by adopting the self-driven polishing head in wafer polishing stations.

• Journal of Electrical Engineering and Technology
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• v.10 no.1
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• pp.295-298
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• 2015

Ozone micro-bubble cleaning system was designed, and made to develop a unique technique to clean wafers by using ozone micro-bubbles. The ozone micro-bubble cleaning system consisted of loading, cleaning, rinsing, drying and un-loading zones, respectively. In case of the cleaning the silicon wafers of a solar cell, more than 99 % of cleaning efficiency was obtained by dipping the wafers at 10 ppm of ozone for 10 minutes. Both of long cleaning time and high ozone concentration in the wet-solution with ozone micro-bubbles reduced cleaning efficiency because of the re-sorption of debris. The cleaning technique by ozone micro-bubbles can be also applied to various wafers for an ingot and LED as an eco-friendly method.

• Journal of the Korean Society for Precision Engineering
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• v.27 no.2
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• pp.13-19
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• 2010

Due to the rapid spread of mobile handheld devices, industrial demands for micro-scale holes with a diameter of even smaller than $10{\mu}m$ in sapphire/silicon wafers have been increasing. Holes in sapphire wafers are for heat dissipation from LEDs; and those in silicon wafers for interlayer communication in three-dimensional integrated circuit (IC). We have developed a sapphire wafer driller equipped with a 532nm laser in which a cooling chuck is employed to minimize local heat accumulation in wafer. Through the optimization of process parameters (pulse energy, repetition rate, number of pulses), quality holes with a diameter of $30{\mu}m$ and a depth of $100{\mu}m$ can be drilled at a rate of 30holes/sec. We also have developed a silicon wafer driller equipped with a 355nm laser. It is able to drill quality through-holes of $15{\mu}m$ in diameter and $150{\mu}m$ in depth at a rate of 100holes/sec.

• Journal of the Semiconductor & Display Technology
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• v.13 no.3
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• pp.21-25
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• 2014

The texturing is one of the most important processes for high efficiency crystalline silicon solar cells. The rear side flatness of silicon solar cell is very important for increasing the light reflectance and forming uniform back surface field(BSF) region in manufacturing high efficiency crystalline silicon solar cells. We investigated texturing difference between front and rear side of wafer by texturing of two adhered wafers. As a result, the flatter rear side was obtained by forming less pyramid size compared to the front side and improved reflectance of long wavelength and back surface field(BSF) region were also achieved. Therefore, the texturing of two adhered wafers can be expected to improve the efficiency of silicon solar cells due to increased short circuit current(Isc).

• Journal of the Korean institute of surface engineering
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• v.32 no.3
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• pp.235-238
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• 1999

Silicon dioxide films were prepared by anodizing silicon wafers in an ethylene $glycol+HNO_3(0.04{\;}N)$ at 20 to $70^{\circ}C$. The voltage between silicon anode and platinum cathode was measured during this process. Under the constant current electrolysis, the voltage increased with oxide film growth. The transition time at which the voltage reached the predetermined value depended on the temperature of the electrolyte. After the time of electrolysis reached the transition time, the anodization was changed the constant voltage mode. The depth profile of oxide film/Si substrate was confirmed by XPS analysis to study the influence of the electrolyte temperature on the anodization. Usually, the oxide-silicon peaks disappear in the silicon substrate, however, this peak was not small at $45^{\circ}C$ in this region.