• 한국윤활학회:학술대회논문집
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• 한국윤활학회 2002년도 proceedings of the second asia international conference on tribology
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• pp.433-434
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• 2002

Chemical mechanical polishing refers to a process by which silicon and partially-processed integrated circuits (IC's) built on silicon substrates are polished to produce planar surfaces for the continued manufacturing of IC's. Chemical mechanical polishing is done by pressing the silicon wafer, face down, onto a rotating platen that is covered by a rough polyurethane pad. During rotation, the pad is flooded with a slurry that contains nanoscale particles. The pad deforms and the roughness of the surface entrains the slurry into the interface. The asperities contact the wafer and the surface is polished in a three-body abrasion process. The contact of the wafer with the 'soft' pad produces a unique elastohydrodynamic situation in which a suction force is imposed at the interface. This added force is non-uniform and can be on the order of the applied pressure on the wafer. We have measured the magnitude and spatial distribution of this suction force. This force will be described within the context of a model of the sliding of hard surfaces on soft substrates.

• 디지털콘텐츠학회 논문지
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• 제3권1호
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• pp.113-122
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• 2002

반도체와 관련한 실리콘웨이퍼의 평탄도는 양질의 웨이퍼를 보증하는 가장 중요한 요소이다. 따라서 평탄도(flatness)를 측정하고 제어하는 Polishing이라는 공정은 웨이퍼 생산의 여러 라인중 특별히 중요시 되는 과정이며 현재 이 공정에서는 담당 엔지니어가 웨이퍼의 모형을 모니터에서 육안으로 관찰하여 판단하고 평탄도를 높이기 위한 제어를 하고 있다. 그러나 사람에 의한 것이므로 많은 경험이 필요하고 일일이 체크해야하는 번거로움이 있다. 본 연구는 이러한 비효율적인 작업의 효율화를 위해 이루어 졌으며 Polishing 공정에 있어 평탄도를 사람이 아닌 시스템에 의해 자동으로 측정하여 제어하는 알고리즘을 제안한다. 여기서 제안한 시스템은 보간 다항식을 이용하여 웨이퍼 전역의 두께를 추정하고 Polishing공정에서 평탄도를 높이기 위해 제어 가능한 모형별로 분류할 수 있도록 하였다.

• 한국태양에너지학회:학술대회논문집
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• 한국태양에너지학회 2011년도 춘계학술발표대회 논문집
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• pp.101-104
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• 2011

Many studies in crystalline silicon solar cell fabrication have been focused on high efficiency and low cost. In this paper, we carried out the doping procedure by varying the silicon wafer thicknesses and sheet resistance. The silicon wafers with various thicknesses were obtained by shiny etching and texturing. The thicknesses of wafers were 100, 120, 150, and $180{\mu}m$. The emitter layer formed by $POCl_3$ doping process had sheet resistance with 40 and $80{\Omega}/sq$ for selective emitter application. This experiment indicated wafer thickness did not influence sheet resistance but lifetime was strongly effected.

• 청정기술
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• 제18권1호
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• pp.43-50
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• 2012

태양전지 제조공정 중 잉곳의 절삭공정 후 진행되는 태양광 실리콘 웨이퍼 세정에 관한 연구를 수행하였다. 태양광 실리콘 웨이퍼는 잉곳의 생산방법에 따라 단결정과 다결정 웨이퍼로 분류되고, 절삭 방법에 따라서는 슬러리로 절삭한 웨이퍼와 다이아몬드 와이어로 절삭한 웨이퍼로 구분할 수 있으며, 이의 방법들에 따라 웨이퍼 표면과 오염원이 달라질 수 있다. 본 연구에서는 세정대상물에 따라 오염원과 웨이퍼 표면의 특성을 관찰하였고 적합한 세정제를 개발하여 물성 및 세정성을 평가하여 적용성을 확인하고자 하였다. 개발된 세정제로 세정한 웨이퍼는 XPS 분석결과 잔류 오염물질이 관찰되지 않았으며, 표면조직화 후 균일한 패턴을 형성함을 확인할 수 있었다. 또한, 개발된 세정제를 웨이퍼 생산현장에서 테스트를 진행하여 기존 세정제보다 우수한 세정결과를 확보하였다.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 1997년도 춘계학술대회 논문집
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• pp.1058-1062
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• 1997

Development of laser induced chemical etching technologt with KrF laser are carried out in this study for micromachining of silicon wafer. The paper is devoted to experimental identification of excimer laser induced mechanism of silicon under chlorine pressures(0.02~500torr). Experimental results on pulsed KrF excimer laser etching of silicon in chorine atmosphere are presented. Etching rate dependency on laser fluence and chlorine pressure are discussed on the basis of experimental analysis, it is concluded that accurate digital micro machining process of silicon wafer can achieved by KrF laser induced chemical etching technology.

• 조명전기설비학회논문지
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• 제21권5호
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• pp.106-111
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• 2007

반도체 공정에서 각 단계별 과정을 거친 후 dechucking시 wafer가 ESC(Electrostatic Chuck)로부터 방전되지 못하고, 잔류되어 있는 극성을 띤 전하(Electric charge)들에 의해 wafer와 ESC사이에 인력이 발생하여 wafer의 sliding, popping 및 wafer broken 등의 문제가 발생한다. 본 논문에서는 wafer와 ESC의 구성을 capacitor를 이용하여 modeling하고, PSpice를 사용하여 chucking system에 의한 wafer의 대전 현상을 모의하고 그 결과를 바탕으로 잔류전하를 방전시키기 위한 여러 가지 방법을 검토하여 최적의 잔류전하 제거 기법을 제시한다. 즉 별도의 전압원을 사용하여 (+)와 (-)를 교번하는 구형파를 인가함과 아울러 일정시간 동안 Plasma내에서 스위칭시킴으로써 ESC나 wafer에 charge되어 있는 극성을 띤 전하들을 중화(Neutralize) 시키도록 하였다. 그리고 이를 실제 하드웨어로 구현하여 실 공정에 적용한 결과를 제시한다.

• 한국정밀공학회지
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• 제21권10호
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• pp.26-33
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• 2004

Ultra precision grinding technology has been developed from the refinement of the abrasive, the development of high stiffness equipment and grinding skill. The conventional wafering process which consists of lapping, etching, 1 st, 2nd and 3rd polishing has been changed to the new process which consists of precision surface grinding, final polishing and post cleaning. Especially, the ultra precision grinding of wafer improves the flatness of wafer and the efficiency of production. Furthermore, it has been not only used in bare wafer grinding, but also applied to wafer back grinding and SOI wafer grinding. This paper focuses on the flatness of the ground wafer. Generally, the ground wafer has concave pronto because of the difference of wheel path density, grinding temperature and elastic deformation of the equipment. Wafer tilting is applied to avoid non-uniform material removal. Through the geometric analysis of wafer grinding process, the profile of the ground wafer is predicted by the development of profile simulator.

• 대한기계학회:학술대회논문집
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• 대한기계학회 2007년도 춘계학술대회B
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• pp.2032-2037
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• 2007

Numerical analysis was conducted to investigate the atomic layer deposition(ALD) of silicon nitride using silane and ammonia as precursors. The present study simulated the surface reactions for as-deposited $Si_3N_4$ as well as the kinetics for the reactions of $SiH_4$ and $NH_3$on the semiconductor wafer. The present numerical results showed that the ALD process is dependent on the activation constant. It was also shown that the low activation constant leads to the self-limiting reaction required for the ALD process. The inlet and wafer temperatures were 473 K and 823 K, respectively. The system pressure is 2 Torr.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1992년도 하계학술대회 논문집 B
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• pp.850-853
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• 1992

A cryogenic electron cyclotron resonance plasma etching system has been built to study wafer-temperature in the silicon etching characteristics. The wafer temperature was controlled from -150 to +30 $^{\circ}C$ during etching using the liquid nitrogen cooled helium gas. Although silicon was etched isotropically in $SF_6$ plasma at room temperatures, we found that it is possible to suppress the etch undercut in Si by reducing a substrate temperature without side wall passivation. In addition, the selectivity of silicon to photoresist was improved considerably at a low wafer temperature. Etch rates, anisotropy and selectivity to photo resist are measured as a function of the wafer temperature in the region of -125 $\sim$ 25$^{\circ}C$ and rf bias power of 20W $\sim$ 80W.

• 한국공작기계학회논문집
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• 제11권5호
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• pp.58-64
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• 2002

Mirror surface finish of Si-wafers has been achieved by rotary in-feed machining with cup-type wheels in ELID grinding. But the diameter of the workpiece is limited with the diameter of the grinding wheel in the in-feed machining method. In this study, some finding experiments by the rotary surface grinding machine with straight type wheels were conducted, by which the possible grinding area of the workpiece is independent of the diameter of the wheels. For the purpose of investigating the grinding characteristics of large scale diametrical silicon wafer, grinding conditions such as rotation speed of grinding wheels and revolution of workpieces are varied, and grinding machine used in this experiment is rotary type surface grinding m/c equipment with an ELID unit. The surface ground using the SD8000 wheels showed that mirror like surface roughness can be attained near 2~6 nm in Ra.