• Title/Summary/Keyword: Silicon vapor

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Multiple-inputs Dual-outputs Process Characterization and Optimization of HDP-CVD SiO2 Deposition

  • Hong, Sang-Jeen;Hwang, Jong-Ha;Chun, Sang-Hyun;Han, Seung-Soo
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.11 no.3
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    • pp.135-145
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    • 2011
  • Accurate process characterization and optimization are the first step for a successful advanced process control (APC), and they should be followed by continuous monitoring and control in order to run manufacturing processes most efficiently. In this paper, process characterization and recipe optimization methods with multiple outputs are presented in high density plasma-chemical vapor deposition (HDP-CVD) silicon dioxide deposition process. Five controllable process variables of Top $SiH_4$, Bottom $SiH_4$, $O_2$, Top RF Power, and Bottom RF Power, and two responses of interest, such as deposition rate and uniformity, are simultaneously considered employing both statistical response surface methodology (RSM) and neural networks (NNs) based genetic algorithm (GA). Statistically, two phases of experimental design was performed, and the established statistical models were optimized using performance index (PI). Artificial intelligently, NN process model with two outputs were established, and recipe synthesis was performed employing GA. Statistical RSM offers minimum numbers of experiment to build regression models and response surface models, but the analysis of the data need to satisfy underlying assumption and statistical data analysis capability. NN based-GA does not require any underlying assumption for data modeling; however, the selection of the input data for the model establishment is important for accurate model construction. Both statistical and artificial intelligent methods suggest competitive characterization and optimization results in HDP-CVD $SiO_2$ deposition process, and the NN based-GA method showed 26% uniformity improvement with 36% less $SiH_4$ gas usage yielding 20.8 ${\AA}/sec$ deposition rate.

Removal of Polymer residue on Graphene by Plasma treatment

  • Yun, Hye-Ju;Jeong, Dae-Seong;Lee, Geon-Hui;Sim, Ji-Ni;Lee, Jeong-O;Park, Jong-Yun
    • Proceedings of the Korean Vacuum Society Conference
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    • 2016.02a
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    • pp.375.2-375.2
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    • 2016
  • 그래핀(Graphene)은 원자 한 층 두께의 얇은 특성에 기인하여 우수한 투과도(~97.3%)를 나타내며, 높은 전자 이동도($200,000cm^2V^{-1}s^{-1}$)로 인하여 전기 전도도가 우수한 2차원 전자소재이다. 또한 유연하고 우수한 기계적 물성을 가지고 있어 실제로 다양한 소자에서 활용되고 있다. 그래핀을 이용하여 다양한 소자로 응용하기 위한 과정 중 하나인 포토리소그래피 공정(Photolithography process)은 원하는 패턴을 만들기 위해 제작하고자 하는 기판 위에 포토레지스트(Photoresist)를 코팅하는 과정을 거치게 된다. 하지만 이러한 과정은 소자 제작에 있어서 포토레지스트 잔여물을 남기게 된다. 그래핀 위에 남은 포토레지스트 잔여물은 그래핀의 우수한 전기적 특성을 저하시켜 소자특성에 불이익을 주게 된다. 본 연구에서는 수소 플라즈마를 이용하여 그래핀 위에 남은 중합체(Polymer) 잔여물을 제거한다. 사용한 그래핀은 화학 기상 증착법(Chemical vapor deposition)을 이용하여 성장시켰으며, PMMA(Poly(methyl methacrylate))를 이용하여 이산화규소(silicon dioxide) 기판에 전사하였다. 그래핀의 손상 없이 중합체 잔여물을 제거하기 위해 플라즈마 처리시간을 15초부터 1분까지 늘려가며 연구를 진행하였으며, 플라즈마 처리 시간에 따른 중합체 잔여물의 제거 정도와 그래핀의 보존 여부를 확인하기 위해 라만 분광법(Raman spectroscopy)과 원자간력현미경(Atomic force microscopy)을 사용하였다. 본 연구 결과를 통해 간단한 플라즈마 처리로 보다 나은 특성의 그래핀 소자를 얻게 됨으로써, 향상된 특성을 가진 그래핀 소자로 산업적 응용 가능성을 높일 수 있을 것이라 생각된다.

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Size, Shape, and Crystal Structure of Silica Particles Generated as By-products in the Semiconductor Workplace (반도체 작업환경 내 부산물로 생성되는 실리카 입자의 크기, 형상 및 결정 구조)

  • Choi, Kwang-Min;Yeo, Jin-Hee;Jung, Myung-Koo;Kim, Kwan-Sick;Cho, Soo-Hun
    • Journal of Korean Society of Occupational and Environmental Hygiene
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    • v.25 no.1
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    • pp.36-44
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    • 2015
  • Objectives: This study aimed to elucidate the physicochemical properties of silica powder and airborne particles as by-products generated from fabrication processes to reduce unknown risk factors in the semiconductor manufacturing work environment. Materials and Methods: Sampling was conducted at 200 mm and 300 mm semiconductor wafer fabrication facilities. Thirty-two powder and airborne by-product samples, diffusion(10), chemical vapor deposition(10), chemical mechanical polishing(5), clean(5), etch process(2), were collected from inner chamber parts from process and 1st scrubber equipment during maintenance and process operation. The chemical composition, size, shape, and crystal structure of silica by-product particles were determined by using scanning electron microscopy and transmission electron microscopy techniques equipped with energy dispersive spectroscopy, and x-ray diffractometry. Results: All powder and airborne particle samples were composed of oxygen(O) and silicon(Si), which means silica particle. The by-product particles were nearly spherical $SiO_2$ and the particle size ranged 25 nm to $50{\mu}m$, and most of the particles were usually agglomerated within a particle size range from approximately 25 nm to 500 nm. In addition, the crystal structure of the silica powder particles was found to be an amorphous silica. Conclusions: The silica by-product particles generated from the semiconductor manufacturing processes are amorphous $SiO_2$, which is considered a less toxic form. These results should provide useful information for alternative strategies to improve the work environment and workers' health.

ILD CMP 공정에서 실리콘 산화막의 기계적 성질이 Scratch 발생에 미치는 영향

  • Jo, Byeong-Jun;Gwon, Tae-Yeong;Kim, Hyeok-Min;Park, Jin-Gu
    • Proceedings of the Materials Research Society of Korea Conference
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    • 2011.10a
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    • pp.23-23
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    • 2011
  • Chemical-Mechanical Planarization (CMP) 공정이란 화학적 반응 및 기계적인 힘이 복합적으로 작용하여 표면을 평탄화하는 공정이다. 이러한 CMP 공정은 반도체 산업에서 회로의 고집적화와 다층구조를 형성하기 위하여 도입되었으며 반도체 제조를 위한 필수공정으로 그 중요성이 강조되고 있다. 특히 최근에는 Inter-Level Dielectric (ILD)의 형성과 Shallow Trench Isolation (STI) 공정에서실리콘 산화막을 평탄화하기 위한 CMP 공정에 대해 연구가 활발히 이루어지고 있다. 그러나 CMP 공정 후 scratch, pitting corrosion, contamination 등의 Defect가 발생하는 문제점이 존재한다. 이 중에서도 scratch는 기계적, 열적 스트레스에 의해 생성된 패드의 잔해, 슬러리의 잔유물, 응집된 입자 등에 의해 표면에 형성된다. 반도체 공정에서는 다양한 종류의 실리콘 산화막이 사용되고 gks이러한 실리콘 산화막들은 종류에 따라 경도가 다르다. 따라서 실리콘 산화막의 경도에 따른 CMP 공정 및 이로 인한 Scratch 발생에 관한 연구가 필요하다고 할 수 있다. 본 연구에서는 scratch 형성의 거동을 알아보기 위하여 boronphoshposilicate glass (BPSG), plasma enhanced chemical vapor deposition (PECVD) tetraethylorthosilicate (TEOS), high density plasma (HDP) oxide의 3가지 실리콘 산화막의 기계적 성질 및 이에 따른 CMP 공정에 대한 평가를 실시하였다. CMP 공정 후 효율적인 scratch 평가를 위해 브러시를 이용하여 1차 세정을 실시하였으며 습식세정방법(SC-1, DHF)으로 마무리 하였다. Scratch 개수는 Particle counter (Surfscan6200, KLA Tencor, USA)로 측정하였고, 광학현미경을 이용하여 형태를 관찰하였다. Scratch 평가를 위한 CMP 공정은 실험에 사용된 3가지 종류의 실리콘 산화막들의 경도가 서로 다르기 때문에 동등한 실험조건 설정을 위해 동일한 연마량이 관찰되는 조건에서 실시하였다. 실험결과 scratch 종류는 그 형태에 따라 chatter/line/rolling type의 3가지로 분류되었다 BPSG가 다른 종류의 실리콘 산화막에 비해 많은 수에 scratch가 관찰되었으며 line type이 많은 비율을 차지한다는 것을 확인하였다. 또한 CMP 공정에서 압력이 증가함에 따라 chatter type scratch의 길이는 짧아지고 폭이 넓어지는 것을 확인하였다. 본 연구를 통해 실리콘 산화막의 경도에 따른 scratch 형성 원리를 파악하였다.

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Effect of TaB2 Addition on the Oxidation Behaviors of ZrB2-SiC Based Ultra-High Temperature Ceramics

  • Lee, Seung-Jun;Kim, Do-Kyung
    • Korean Journal of Materials Research
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    • v.20 no.4
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    • pp.217-222
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    • 2010
  • Zirconium diboride (ZrB2) and mixed diboride of (Zr0.7Ta0.3)B2 containing 30 vol.% silicon carbide (SiC) composites were prepared by hot-pressing at $1800^{\circ}C$. XRD analysis identified the high crystalline metal diboride-SiC composites at $1800^{\circ}C$. The TaB2 addition to ZrB2-SiC showed a slight peak shift to a higher angle of 2-theta of ZrB2, which confirmed the presence of a homogeneous solid solution. Elastic modulus, hardness and fracture toughness were slightly increased by addition of TaB2. A volatility diagram was calculated to understand the oxidation behavior. Oxidation behavior was investigated at $1500^{\circ}C$ under ambient and low oxygen partial pressure (pO2~10-8 Pa). In an ambient environment, the TaB2 addition to the ZrB2-SiC improved the oxidation resistance over entire range of evaluated temperatures by formation of a less porous oxide layer beneath the surface SiO2. Exposure of metal boride-SiC at low pO2 resulted in active oxidation of SiC due to the high vapor pressure of SiO (g), and, as a result, it produced a porous surface layer. The depth variations of the oxidized layer were measured by SEM. In the ZrB2-SiC composite, the thickness of the reaction layer linearly increased as a function of time and showed active oxidation kinetics. The TaB2 addition to the ZrB2-SiC composite showed improved oxidation resistance with slight deviation from the linearity in depth variation.

Process Characteristics of SiOx and SiOxNy Films on a Gas Barrier Layer using Facing Target Sputtering (FTS) System (FTS 장치를 이용한 가스 차단막용 SiOx 및 SiOxNy 박막의 공정특성)

  • Son, Jin-Woon;Park, Yong-Jin;Sohn, Sun-Young;Kim, Hwa-Min
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.22 no.12
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    • pp.1028-1032
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    • 2009
  • In this study, the influences of silicon-based gas barrier films fabricated by using a facing target sputtering(FTS) system on the gas permeability for flexible displays have been investigated. Under these optimum conditions on the $SiO_x$ film with oxygen concentration($O_2/Ar+O_2$) of 3.3% and the $SiO_xN_y$ film with nitrogen concentration($N_2/Ar+O_2+N_2$) of 30% deposited by the FTS system, it was found that the films were grown about 4 times higher deposition rate than that of the conventional sputtering system and showed high transmittance about 85% in the visible light range. Particularly, the polyethylene naphthalate(PEN) substrates with the $SiO_x$ and/or $SiO_xN_y$ films showed the enhanced properties of decreased water vapor transmission rate (WVTR) over $10^{-1}\;g/m^2{\cdot}day$ compared with the PEN substrate without any gas barrier films, which was due to high packing density in the Si-based films with high plasma density by FTS process and/or the denser chemical structure of Si-N bond in the $SiO_xN_y$ film.

Low Temperature Deposition a-SiNx:H Using ICP Source (ICP Source를 이용한 저온 증착 a-SiNx:H 특성 평가)

  • Kang, Sung-Chil;Lee, Dong-Hyeok;So, Hyun-Wook;Jang, Jin-Nyoung;Hong, Mun-Pyo;Kwon, Kwang-Ho
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.24 no.7
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    • pp.532-536
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    • 2011
  • The silicon nitride films were prepared by chemical vapor deposition using inductively coupled plasma. During the deposition, the substrate was heated at $150^{\circ}C$ and power 1,000 W. To evolution low temperature manufacture, we have studied the role of source gases, $SiH_4$, $NH_3$, $N_2$, and $H_2$, to produce Si-N and N-H bond in a-SiNx:H film growth. $SiH_4$, $NH_3$, and $N_2$ flow rate fixed at 100, 10, and 10 sccm, $H_2$ flow rate varied from 0 to 10 sccm by small scale. To get the electrical characteristics, we makes MIM structure, and analysis surface bonding state. Experimental data show that Si-N and N-H bond is increased and hence electrical characteristics is showed 3 MV/cm breakdown-voltage, and leakage-current $10^{-7}\;A/cm^2$.

A study on the nonvolatile memory characteristics of MNOS structures with double nitride layer (2층 질하막 MNOS구조의 비휘발성 기억특성에 관한 연구)

  • 이형욱
    • Electrical & Electronic Materials
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    • v.9 no.8
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    • pp.789-798
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    • 1996
  • The double nitride layer Metal Nitride Oxide Semiconductor(MNOS) structures were fabricated by variating both gas ratio and nitride thickness, and by duplicating nitride deposited and one nitride layer MNOS structure to improve nonvolatile memory characteristics of MNOS structures by Low Pressure Chemical Vapor Deposition(LPCVD) method. The nonvolatile memory characteristics of write-in, erase, memory retention and degradation of Bias Temperature Stress(BTS) were investigated by the homemade automatic .DELTA. $V_{FB}$ measuring system. In the trap density double nitride layer structures were higher by 0.85*10$^{16}$ $m^{-2}$ than one nitride layer structure, and the AVFB with oxide field was linearly increased. However, one nitride layer structure was linearly increased and saturated above 9.07*10$^{8}$ V/m in oxide field. In the erase behavior, the hole injection from silicon instead of the trapped electron emission was observed, and also it was highly dependent upon the pulse amplitude and the pulse width. In the memory retentivity, double nitrite layer structures were superior to one nitride layer structure, and the decay rate of the trapped electron with increasing temperature was low. At increasing the number on BTS, the variance of AVFB of the double nitride layer structures was smaller than that of one nitride layer structure, and the trapped electron retention rate was high. In this paper, the double nitride layer structures were turned out to be useful in improving the nonvolatile memory characteristics.

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Fabrication and Characteristics of Lateral Type Field Emitter Arrays

  • Lee, Jae-Hoon;Kwon, Ki-Rock;Lee, Myoung-Bok;Hahm, Sung-Ho;Park, Kyu-Man;Lee, Jung-Hee
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.2 no.2
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    • pp.93-101
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    • 2002
  • We have proposed and fabricated two lateral type field emission diodes, poly-Si emitter by utilizing the local oxidation of silicon (LOCOS) and GaN emitter using metal organic chemical vapor deposition (MOCVD) process. The fabricated poly-Si diode exhibited excellent electrical characteristics such as a very low turn-on voltage of 2 V and a high emission current of $300{\;}\bu\textrm{A}/tip$ at the anode-to-cathode voltage of 25 V. These superior field emission characteristics was speculated as a result of strong surface modification inducing a quasi-negative electron affinity and the increase of emitting sites due to local sharp protrusions by an appropriate activation treatment. In respect, two kinds of procedures were proposed for the fabrication of the lateral type GaN emitter: a selective etching method with electron cyclotron resonance-reactive ion etching (ECR-RIE) or a simple selective growth by utilizing $Si_3N_4$ film as a masking layer. The fabricated device using the ECR-RIE exhibited electrical characteristics such as a turn-on voltage of 35 V for $7\bu\textrm{m}$ gap and an emission current of~580 nA/l0tips at anode-to-cathode voltage of 100 V. These new field emission characteristics of GaN tips are believed to be due to a low electron affinity as well as the shorter inter-electrode distance. Compared to lateral type GaN field emission diode using ECR-RIE, re-grown GaN emitters shows sharper shape tips and shorter inter-electrode distance.

Fabrication and Its Characteristics of HgCdTe Infrared Detector (HgCdTe를 이용한 Infrared Detector의 제조와 특성)

  • 김재묵;서상희;이희철;한석룡
    • Journal of the Korea Institute of Military Science and Technology
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    • v.1 no.1
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    • pp.227-237
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    • 1998
  • HgCdTe Is the most versatile material for the developing infrared devices. Not like III-V compound semiconductors or silicon-based photo-detecting materials, HgCdTe has unique characteristics such as adjustable bandgap, very high electron mobility, and large difference between electron and hole mobilities. Many research groups have been interested in this material since early 70's, but mainly due to its thermodynamic difficulties for preparing materials, no single growth technique is appreciated as a standard growth technique in this research field. Solid state recrystallization(SSR), travelling heater method(THM), and Bridgman growth are major techniques used to grow bulk HgCdTe material. Materials with high quality and purity can be grown using these bulk growth techniques, however, due to the large separation between solidus and liquidus line on the phase diagram, it is very difficult to grow large materials with minimun defects. Various epitaxial growth techniques were adopted to get large area HgCdTe and among them liquid phase epitaxy(LPE), metal organic chemical vapor deposition(MOCVD), and molecular beam epitaxy(MBE) are most frequently used techniques. There are also various types of photo-detectors utilizing HgCdTe materials, and photovoltaic and photoconductive devices are most interested types of detectors up to these days. For the larger may detectors, photovoltaic devices have some advantages over power-requiring photoconductive devices. In this paper we reported the main results on the HgCdTe growing and characterization including LPE and MOCVD, device fabrication and its characteristics such as single element and linear array($8{\times}1$ PC, $128{\times}1$ PV and 4120{\times}1$ PC). Also we included the results of the dewar manufacturing, assembling, and optical and environmental test of the detectors.

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