• 한국결정성장학회:학술대회논문집
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• 한국결정성장학회 1996년도 The 9th KACG Technical Annual Meeting and the 3rd Korea-Japan EMGS (Electronic Materials Growth Symposium)
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• pp.422-448
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• 1996

Low-temperature epitaxial growth of Si and SiGe layers of Si is one of the important processes for the fabrication of the high-speed Si-based heterostructure devices such as heterojunction bipolar transistors. Low-temperature growth ensures the abrupt compositional and doping concentration profiles for future novel devices. Especially in SiGe epitaxy, low-temperature growth is a prerequisite for two-dimensional growth mode for the growth of thin, uniform layers. UHV-ECRCVD is a new growth technique for Si and SiGe epilayers and it is possible to grow epilayers at even lower temperatures than conventional CVD's. SiH and GeH and dopant gases are dissociated by an ECR plasma in an ultrahigh vacuum growth chamber. In situ hydrogen plasma cleaning of the Si native oxide before the epitaxial growth is successfully developed in UHV-ECRCVD. Structural quality of the epilayers are examined by reflection high energy electron diffraction, transmission electron microscopy, Nomarski microscope and atomic force microscope. Device-quality Si and SiGe epilayers are successfully grown at temperatures lower than 600℃ after proper optimization of process parameters such as temperature, total pressure, partial pressures of input gases, plasma power, and substrate dc bias. Dopant incorporation and activation for B in Si and SiGe are studied by secondary ion mass spectrometry and spreading resistance profilometry. Silicon p-n homojunction diodes are fabricated from in situ doped Si layers. I-V characteristics of the diodes shows that the ideality factor is 1.2, implying that the low-temperature silicon epilayers grown by UHV-ECRCVD is truly of device-quality.

• 한국재료학회지
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• 제10권6호
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• pp.450-455
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• 2000

실리콘 소자가 더욱 미세화되면서, 발생되는 power consumption, crosstalk와 interconnection delay 등을 감소시키기 위해 $SiO_2$ 대신에 저유전 상수막의 적용이 고려되어진다. 본 논문에서는, 저유전 상수 층간 절연막 재료로 유망한 폴리이미드의 식각 특성에 $O_2/SF_6$ 가스가 미치는 영향을 연구하였다. 폴리이미드의 식각률을 SF(sub)6 가스의 첨가에 따라 산소와 hydrocarbon 폴리머 간의 반응을 억제하는 비휘발성 물질은 fluorine 화합물의 형성에 의해 감소되었다. 반면에, 기판 전극의 전압 증가는 물리적인 충격을 통해 식각 공정을 증가시켰다. 또한 작은 량의 SF(sub)6 가스 첨가는 식각 topography에 바람직하였다. 폴리이미드 식각을 위한 $SiO_2$ hard mask 사용은 산소 플라즈마 식각 하에서 효과적이었다(선택비-30). 반면에 $O_2SF_6$ 가스 조성은 식각 선택비를 4로 저하시키게 되었다. 이러한 결과를 기초로, $1-2\mu\textrm{m}$ 선폭을 가진 PI 2610의 식각을 원활히 수행할 수 있었다.

• Current Photovoltaic Research
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• 제3권3호
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• pp.80-84
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• 2015

We suggest new emitter formation method using solid-phase epitaxy (SPE); solid-phase epitaxy emitter (SEE). This method expect simplification and cost reduction of process compared with furnace process (POCl3 or BBr3). The solid-phase epitaxy emitter (SEE) deposited a-Si:H layer by radio-frequency plasma-enhanced chemical vapor deposition (RF-PECVD) on substrate (c-Si), then thin layer growth solid-phase epitaxy (SPE) using rapid thermal process (RTP). This is possible in various emitter profile formation through dopant gas ($PH_3$) control at deposited a-Si:H layer. We fabricated solar cell to apply solid-phase epitaxy emitter (SEE). Its performance have an effect on crystallinity of phase transition layer (a-Si to c-Si). We confirmed crystallinity of this with a-Si:H layer thickness and annealing temperature by using raman spectroscopy, spectroscopic ellipsometry and transmission electron microscope. The crystallinity is excellent as the thickness of a-Si layer is thin (~50 nm) and annealing temperature is high (<$900^{\circ}C$). We fabricated a 16.7% solid-phase epitaxy emitter (SEE) cell. We anticipate its performance improvement applying thin tunnel oxide (<2nm).

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2008년도 하계학술대회 논문집 Vol.9
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• pp.202-202
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• 2008

실리콘 기판 위에 성장된 세륨 산화막(CeO2)은 고품질의 SOI(Silicon on Insulator)나 혹은 안정한 캐패시터 소자와 같은 반도체 소자에 대한 응용 가능성이 높아 여러 연구가 진행되어 왔다. 세륨 산화막은 형석 구조, 다시 말해서 대칭적인 큐빅 구조이며 화학적으로 안정한 물질이다. 또한, 세륨 산화막의 격자상수 (a = $5.411\AA$)는 실리콘의 격자상수 (a = $5.430\AA$) 와 비슷하며 큰 밴드갭(6eV) 및 높은 유전상수 ($\varepsilon$ = 26), 높은 열적 안전성을 지니고 있어 실리콘 기판에 사용된 기존 절연막인 사파이어나 질코늄 산화막보다 우수한 특성을 지니고 있다. 본 논문에서는 스퍼터링을 이용하여 세륨 산화막을 실리콘 기판 위에 형성하면서 기판가열 온도 조건을 각각 상온, $100^{\circ}C$, $200^{\circ}C$로 설정하였으며, 세륨 산화막의 증착 두께 조건을 각각 80nm, 120nm로 설정한 다음 퍼니스를 이용하여 $1100^{\circ}C$에서 1시간 동안 열처리를 거친 세륨 산화막의 결정화 형태 및 박막의 막질 상태를 각각 X선 회절 장치 (XRD) 및 주사전자현미경 (SEM)으로 관찰하였다.

• 전기전자학회논문지
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• 제23권2호
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• pp.594-598
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• 2019

HfZnO 박막 위 패턴 전사 기법을 이용하여 기존의 러빙법을 대체하는 배향 공정에 대하여 연구하였다. 정렬 패턴은 레이저 간섭 리소그래피를 이용하여 실리콘 웨이퍼 위에 제작하였다. 졸겔 공정을 이용하여 HfZnO 용액을 제작하였고, 유리기판 위에 스핀코팅하였다. 미리 제작한 정렬패턴을 스핀코팅된 HfZnO 위에 올려놓고, $100^{\circ}C$에서 30분간 소성하였다. HfZnO 박막에 평행한 그루브가 형성되었음을 atomic force microscopy 와 scanning electron microscopy로부터 확인할 수 있었다. HfZnO 박막을 이용하여 액정 셀을 제작하였으며, POM 분석으로부터 액정이 균일하게 정렬되었음을 확인할 수 있었다. 액정은 $0.25^{\circ}$의 프리틸트 각을 가졌으며, 수평배향 특성을 보여주었다. 액정 분자는 평행한 그루브에 의한 HfZnO 박막 표면 이방성에 의하여 균일하게 정렬되었음을 확인할 수 있었다.

• 한국항해항만학회:학술대회논문집
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• 한국항해항만학회 2000년도 추계학술대회논문집
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• pp.29-32
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• 2000

Cerium oxide thin film has been proposed as a buffer layer between the ferroelectric film and the Si substrate in Metal-Ferroelectric-Insulator-Silicon (MFIS ) structures for ferroelectric random access memory (FRAM) applications. In this study, CeO$_2$thin films were etched with Cl$_2$/Ar gas combination in an inductively coupled plasma (ICP). The highest etch rate of CeO$_2$film is 230 $\AA$/min at Cl$_2$/(Cl$_2$+Ar) gas mixing ratio of 0.2. This result confirms that CeO$_2$thin film is dominantly etched by Ar ions bombardment and is assisted by chemical reaction of Cl radicals. The selectivity of CeO$_2$to YMnO$_3$was 1.83. As a XPS analysis, the surface of etched CeO$_2$thin films was existed in Ce-Cl bond by chemical reaction between Ce and Cl. The results of XPS analysis were confirmed by SIMS analysis. The existence of Ce-Cl bonding was proven at 176.15 (a.m.u.).

• 한국신재생에너지학회:학술대회논문집
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• 한국신재생에너지학회 2007년도 춘계학술대회
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• pp.335-338
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• 2007

Cost effectiveness is an important parameter for producing DSSCs as compared to the widely used conventional silicon based solar cells. A fluorine-doped tin oxide (FTO) substrate coated with a catalytic amount of platinum is used as counter electrode in dye-sensitized solar cell. Carbonaceous materials are quite attractive to replace platinum due to their high electronic conductivity, corrosion resistance towards $I_{2}$, good catalytic effect and low cost. In this paper, the unit DSSCs with Pt and CNT as a counter electrode were connected in series-parallel externally, then the current-voltage curves were investigated to find out the connection characteristics of the DSSC with CNT counter electrode. The connection characteristics of the DSSC with CNT counter electrode is superior to that of the DSSC with Pt counter electrode. And a parallel connection of the DSSC with CNT counter electrode has higher efficiency than a series connection of that.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2002년도 하계학술대회 논문집
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• pp.190-193
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• 2002

The processing technology of organic thin-film transistors (Ons) performances have improved fur the last decade. Gate insulator layer has generally used inorganic layer, such as silicon oxide which has properties of a low electrical conductivity and a high breakdown field. However, inorganic insulating layers, which are formed at high temperature, may affect other layers termed on a substrate through preceding processes. On the other hand, organic insulating layers, which are formed at low temperature, dose not affect pre-process. Known wet-processing methods for fabricating organic insulating layers include a spin coating, dipping and Langmuir-Blodgett film processes. In this paper, we propose the new dry-processing method of organic gate dielectric film in field-effect transistors. Vapor deposition polymerization (VDP) that is mainly used to the conducting polymers is introduced to form the gate dielectric. This method is appropriate to mass production in various end-user applications, for example, flat panel displays, because it has the advantages of shadow mask patterning and in-situ dry process with flexible low-cost large area displays. Also we fabricated four by four active pixels with all-organic thin-film transistors and phosphorescent organic light emitting devices.

• 한국전기전자재료학회논문지
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• 제28권8호
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• pp.481-485
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• 2015

We investigated the effects of annealing on the electrical and thermal properties of ZTO/4H-SiC heterojunction diodes. A ZTO thin film layer was grown on p-type 4H-SiC substrate by using solution process. The ZTO/SiC heterojunction structures annealed at $500^{\circ}C$ show that $I_{on}/I_{off}$ increases from ${\sim}5.13{\times}10^7$ to ${\sim}1.11{\times}10^9$ owing to the increased electron concentration of ZTO layer as confirmed by capacitance-voltage characteristics. In addition, the electrical characterization of ZTO/SiC heterojunction has been carried out in the temperature range of 300~500 K. When the measurement temperature increased from 300 K to 500 K, the reverse current variation of annealed device is higher than as-grown device, which is related to barrier height in the ZTO/SiC interface. It is shown that annealing process is possible to control the electrical characteristics of ZTO/SiC heterojunction diode.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2010년도 제39회 하계학술대회 초록집
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• pp.180-180
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• 2010

The design and implementation of high rate deposition process and anti-scratch property of silicon oxide film by PECVD with UHF power were investigated according to the effect of UHF input power with HF bias. New regime of high rate deposition of SiOx films by hybrid plasma process was investigated. The dissociation of OMCTS (C8H24Si4O4) precursor was controlled by plasma processes. SiOx films were deposited on polyethylene terephthalate (PET) and polycarbonate substrate by plasma enhanced chemical vapor deposition (PECVD) using OMCTS with oxygen carrier gas. As the input energy increased, the deposition rate of SiOx film increased. The plasma diagnostics were performed by optical emission spectrometry. The deposition rate was characterized by alpha-step. The mechanical properties of the coatings were examined by nano-indenter and pencil hardness, respectively. The deposition rate of the SiOx films could be controlled by the appropriate intensity of excited neutrals, ionized atoms and UHF input power with HF bias at room temperature, as well as the dissociation of OMCTS.