• 한국정보통신학회:학술대회논문집
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• 한국정보통신학회 2016년도 춘계학술대회
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• pp.166-168
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• 2016

이 논문은 포켓 구조 터널링 전계효과 트랜지스터의 구조에 대한 여러 가지 조건을 소개한다. 포켓의 길이는 길어질수록 $I_{on}$이 더 증가하고, 포켓의 두께는 감소할수록 $I_{on}$이 증가하고, 3nm 보다 얇아질 때 SS는 증가한다. 게이트 절연체는 고유전율 물질을 사용하는 것이 적절하다.

• 센서학회지
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• 제5권4호
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• pp.41-46
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• 1996

변압기 절연유중 용존수소를 감지하기 위해 Pd/Pt 게이트 MISFET 센서를 제조하고 그 특성을 조사하였다. 동일 칩안에 내장형 히터와 온도측정용 다이오드를 제조하고 MISFET의 전압 드리프트를 줄이기 위해 차동형구조로 하였다. 수소유입 드리프트를 줄이기 위해, 양쪽 FET의 게이트 절연층을 실리콘 산화막과 실리콘 질화막의 2중 구조로 하였다. 수소감지막의 블리스터를 줄이기 위해 Pd/Pt 2중 금속층을 증착하였다. 제조된 센서의 변압기 절연유에 대한 수소감지 특성은 40mV/10ppm 감도와 0.14mV/day 안정도를 보였다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1995년도 추계학술대회 논문집 학회본부
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• pp.367-369
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• 1995

An SOI LDMOS(Silicon-On-Insulator Lateral Double diffused MOSPET) with a tapered field plate is proposed and investigated in terms of the breakdown voltage and on-resistance using 2-D simulator, MEDICI. The results of conventional SOI LDMOS with a stepped field plate are reported for the comparison. Simulated breakdown voltage of the proposed LDMOS is found to be higher than that of conventional LDMOS since surface electric field can be reduced due to the field plate over the tapered oxide. On-resistance of proposed LDMOS is found to be lower than that of conventional LDMOS by 10%.

• Transactions on Electrical and Electronic Materials
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• 제2권4호
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• pp.30-32
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• 2001

In this paper, a new silicon-on-insulator (SOI) lateral insulated gate bipolar transistor (LIGBT) is proposed to improve the latch-up performance without current path underneath the n$^{+}$ cathode region. The improvement of latch-up performance is verified using the two- dimensional simulator MEDICI and the simulation results on the latch-up current density are 4468 A/cm2 for the proposed LIGBT and 1343 A/$\textrm{cm}^2$ for the conventional LIGBT. The proposed SOI LIGBT exhibits 3 times larger latch-up capability than the conventional SOI LIGBT.T.

• 한국반도체및디스플레이장비학회:학술대회논문집
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• 한국반도체및디스플레이장비학회 2006년도 추계학술대회 발표 논문집
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• pp.10-13
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• 2006

This paper describes on the fabrication and characteristics of a 3C-SiC (Silicon Carbide) micro pressure sensor for harsh environment applications. The implemented micro pressure sensor used 3C-SiC thin-films heteroepitaxially grown on SOI (Si-on-insulator) structures. This sensor takes advantages of the good mechanical properties of Si as diaphragms fabricated by D-RIE technology and temperature properties of 3C-SiC piezoresistors. The fabricated pressure sensors were tasted at temperature up to $250^{\circ}C$ and indicated a sensitivity of 0.46 mV/V*bar at room temperature and 0.28 mV/V*bar at $250^{\circ}C$. The fabricated 3C-Sic/SOI pressure sensor presents a high-sensitivity and excel lent temperature stability.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2008년도 추계학술대회 논문집 Vol.21
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• pp.274-274
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• 2008

This paper describes on the fabrication and characteristics of a 3C-SiC (Silicon Carbide) micro pressure sensor for harsh environment applications. The implemented micro pressure sensor used 3C-SiC thin-films heteroepitaxially grown on SOI (Si-on-insulator) structures. This sensor takes advantages of the good mechanical properties of Si as diaphragms fabricated by D-RIE technology and temperature properties of 3C-SiC piezoresistors. The fabricated pressure sensors were tasted at temperature up to $250^{\circ}C$ and indicated a sensitivity of 0.46 mV/V*bar at room temperature and 0.28 mV/V*bar at $250^{\circ}C$. The fabricated 3C-SiC/SOI pressure sensor presents a high-sensitivity and excellent temperature stability.

• 한국전기전자재료학회논문지
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• 제21권8호
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• pp.711-714
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• 2008

Metal-oxide-semiconductor (MOS) capacitors were fabricated to investigate the plasma damage caused by reactive ion etching (RIE) on (100) oriented silicon-on-insulator (SOI) substrates. The thickness of the top-gate oxide, SOI, and buried oxide layers were 10 nm, 50 nm, and 100 nm, respectively. The MOS/SOI capacitors with an etch-damaged SOI layer were characterized by capacitance-voltage (C-V) measurements and compared to the sacrificial oxidation treated samples and the reference samples without etching. The measured C-V curves were compared to the numerical results from corresponding 2-dimensional (2-D) structures by using a Silvaco Atlas simulator.

• JSTS:Journal of Semiconductor Technology and Science
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• 제7권2호
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• pp.102-109
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• 2007

We propose and experimentally demonstrate a ring resonator with sharp U-turns fabricated on a silicon-on-insulator (SOI) substrate; the resonator was designed as a key part of an optical, dynamic data storage device. We discuss the optical properties of the fabricated ring resonator from the viewpoint of equi-frequency-contour behavior in a dispersion space. We successfully characterize its optical characteristics on the basis of photonic crystal physics. It is suggested that the photonic ring resonator will be applicable to optical, dynamic memory devices for optical communication systems.

• Journal of the Optical Society of Korea
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• 제18권2호
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• pp.101-109
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• 2014

In this paper, four apodization functions are proposed for silicon-on-insulator (SOI) strip waveguides with sidewall-corrugated gratings. The effects of apodization functions on the full width at half maximum (FWHM), the side-lobe level, and the reflectivity of the reflection spectrum are studied using the coupled-mode theory (CMT) and the transfer-matrix method (TMM). The results show that applying proposed apodization functions creates very good filtering characteristics. Among investigated apodized waveguides, the apodization functions of Polynomial and z-power have the best performance in reducing side-lobes, where the side-lobe oscillations are entirely removed. Four functions are also used for precise adjustment of the bandwidth. Simulation results show that the minimum and maximum values of the FWHM are 0.74 nm and 8.48 nm respectively. In some investigated functions, changing the apodization parameters decreases the reflectivity which is compensated by increasing the grating length.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1999년도 추계학술대회 논문집
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• pp.598-601
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• 1999

There is currently considerable interest in the applications of conjugated polymers, oligomers and small molecules for thin-film electronic devices. Organic materials have potential advantages to be utilized as semiconductors in field effect transistor and light emitting didoes. In this study, Pentacene thin film transistors(TFTs) were fabricated on glass substrate. Aluminum and Gold wei\ulcorner used fur the gate and source/drain electrodes. Silicon dioxde was deposited as a gate insulator by PECVD and patterned by R.I.E. The semiconductor layer of pentacene was thermally evaporated in vaccum at a pressure of about 10$^{-8}$ Torr and a deposition rate 0.3$\AA$/sec. The fabricated devices exhibited the field-effect mobility as large as 0.07cm$^2$/Vs and on/off current ratio larger than 10$^{7}$