• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.06a
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• pp.21-21
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• 2007

Strained silicon 기술은 MOSFET 채널 내 캐리어 이동도를 향상시켜 집적회로의 성능을 향상시키는 기술이다. 최근에는 strained 실리콘 기술과 SOI(silicon On Insulator) 기술을 접목시켜 집적회로 소자의 특성을 더욱 향상시킨 SSOI(Strained Silicon On Insulator) 기술이 연구되고 있다. 본 연구에서는 pseudo MOSFET 측정법을 이용하여 strained SOI 웨이퍼의 전기적 특성 분석을 행하였다. pseudo MOSFET 측정법은 SOI 웨이퍼의 전기적 특성분석을 위해 고안된 방법으로써 산화, 도핑 등의 소자 제조 공정 없이도 SOI 표면 실리콘층의 이동도와 매몰산화막과의 계면 특성 등을 분석해 낼 수 있는 기술이다. 표면 실리콘층의 두께와 매몰산화막의 두께가 각각 60nm, 150nm인 SOI 웨이퍼와 동일한 막 두께를 가지며 표면 실리콘층이 strained silicon인 SSOI 웨이퍼를 제작하여 그 특성을 비교 분석하였다. Pseudo MOSFET 측정 결과 Strained SOI 웨이퍼에서 표면 실리콘총 내의 전자 이동도가 일반적인 SOI 웨이퍼보다 약 25% 향상되었으며 정공 이동도나 매몰산화막의 계면 트랩밀도는 큰 차이를 보이지 않았다.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.07a
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• pp.874-877
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• 2001

SOI(Silicon-On-Insulator) technology is proposed as an alternative to bulk silicon for MEMS(Micro Electro Mechanical System) manufacturing. In this paper, we fabricated the SOI wafer with uniform active layer thickness by silicon direct bonding and mechanical polishing processes. Specially-designed electrostatic bonding system is introduced which is available for vacuum packaging and silicon-glass wafer bonding for SOG(Silicon On Glass) wafer. We demonstrated thermopile sensor and RF resonator using the SOI wafer, which has the merits of simple process and uniform membrane fabrication.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.06a
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• pp.95-96
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• 2009

A fully depleted capacitorless 1-transistor dynamic random access memory (FD 1T-DRAM) based on a sSOI strained-silicon-on-insulator) wafer was investigated. The fabricated device showed excellent electrical characteristics of transistor such as low leakage current, low subthreshold swing, large on/off current ratio, and high electron mobility. The FD sSOI 1T-DRAM can be operated as memory device by the floating body effect when the substrate bias of -15 V is applied, and the FD sSOI 1T-DRAM showed large sensing margin and several milli seconds data retention time.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.11a
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• pp.163-166
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• 2003

The electrothermal simulation of high voltage LIGBT(Lateral Insulated Gate Bipolar Transistor) in thin Silicon on insulator (SOI) and Silicon on sapphire (SOS) for thermal conductivity and sink is performed by means of MEDICI. The finite element simulations demonstrate that the thermal conductivity of the buried oxide is an important parameter for the modeling of the thermal behavior of silicon-on-insulator (SOI) devices. In this paper, using for SOI LIGBT, we simulated electrothermal for device that insulator layer with $SiO_2\;and\;Al_2O_3$ at before and after latch up to measured the thermal conductivity and temperature distribution of whole device and verified that SOI LIGBT with $Al_2O_3$ insulator had good thermal conductivity and reliability

• Proceedings of the Optical Society of Korea Conference
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• 2003.02a
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• pp.172-173
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• 2003

SOI (Silicon on insulator) 웨이퍼를 이용하여 제작된 전자소자는 고온에서 동작이 안정될 뿐만 아니라 초고속 동작이 가능하고, 사용 소비전력이 낮고, 단위 소자의 집적 효율이 우수해 활발한 연구가 이루어지고 있다. 최근에 초고속 광소자와 단위 광소자들의 집적을 위해 Si 이외의 GaAs, InP, SIC 등의 반도체 박막을 절연층 위에 만드는 연구가 많이 진행되고 있다 따라서 초기에 절연체 위에 실리콘 박막을 형성하는 Silicon on insulator (SOI) 기술은 다양한 종류의 반도체 박막을 절연체 위에 형성하는 Semiconductor on insulator로 SOI의 의미가 확장되고 있다. (중략)

• 한국컴퓨터산업교육학회:학술대회논문집
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• 2003.11a
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• pp.79-82
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• 2003

The electrothermal simulation of high voltage LIGBT(Lateral Insulated Gate Bipolar Transistor) in thin Silicon on insulator (SOI) and Silicon on sapphire (SOS) for thermal conductivity and sink is performed by means of MEDICI. The finite element simulations demonstrate that the thermal conductivity of the buried oxide is an important parameter for the modeling of the thermal behavior of silicon-on-insulator (SOI) devices. In this paper, using for SOI LIGBT, we simulated electrothermal for device that insulator layer with $SiO_2$ and $Al_2O_3$ at before and after latch up to measured the thermal conductivity and temperature distribution of whole device and verified that SOI LIGBT with $Al_2O_3$ insulator had good thermal conductivity and reliability.

• JSTS:Journal of Semiconductor Technology and Science
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• v.8 no.3
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• pp.264-275
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• 2008

Electron mobility has been investigated theoretically in undoped double-gate (DG) MOSFETs of different channel architectures: a relaxed-Si DG SOI, a strained-Si (sSi) DG SSOI (strained-Si-on-insulator, containing no SiGe layer), and a strained-Si DG SGOI (strained-Si-on-SiGe-on-insulator, containing a SiGe layer) at 300K. Electron mobility in the DG SSOI device exhibits high enhancement relative to the DG SOI. In the DG SGOI devices the mobility is strongly suppressed by the confinement of electrons in much narrower strained-Si layers, as well as by the alloy scattering within the SiGe layer. As a consequence, in the DG SGOI devices with thinnest strained-Si layers the electron mobility may drop below the level of the relaxed DG SOI and the mobility enhancement expected from the strained-Si devices may be lost.

• JSTS:Journal of Semiconductor Technology and Science
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• v.9 no.3
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• pp.136-147
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• 2009

In this paper we analyze the influence of source/drain (S/D) extension region design for minimizing short channel effects (SCEs) in 25 nm gate length single and double gate Silicon-on-Insulator (SOI) and Germanium-on-Insulator (GOI) MOSFETs. A design methodology, by evaluatingm the ratio of the effective channel length to the natural length for the different devices (single or double gate FETs) and technology (SOI or GOI), is proposed to minimize short channel effects (SCEs). The optimization of non-overlapped gate-source/drain i.e. underlap channel architecture is extremely useful to limit the degradation in SCEs caused by the high permittivity channel materials like Germanium as compared to that exhibited in Silicon based devices. Subthreshold slope and Drain Induced Barrier Lowering results show that steeper S/D gradients along with wider spacer regions are needed to suppress SCEs in GOI single/double gate devices as compared to Silicon based MOSFETs. A design criterion is developed to evaluate the minimum spacer width associated with underlap channel design to limit SCEs in SOI/GOI MOSFETs.

• Electrical & Electronic Materials
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• v.7 no.4
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• pp.331-340
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• 1994

Polysilicon on insulator has been recrystallized by zone melting recrystallization method with graphite strip heaters. Experiments are performed with non-seed SOI structures. When the capping layer thickness of Si$\_$3/N$\_$4//SiO$\_$2/ is 2.0.mu.m, grain boundaries are about 120.mu.m spacing and protrusions reduced. After the seed SOI films are annealed at 1100.deg. C in NH$\_$3/ ambient for 3 hours, the recrystallized silicon surface has convex shape. After ZMR process, the tensile stress is 2.49*10$\^$9/dyn/cm$\^$2/ and 3.74*10$\^$9/dyn/cm$\^$2/ in the seed edge and seed center regions. The phenomenon of convex shape and tensile stress difference are completely eliminated by using the PSG/SiO$\_$2/ capping layer. The characterization of SOI films are showed that the SOI films are improved in wetting properties. N channel SOI MOSFET has been fabricated to investigate the electrical characteristics of the recrystallized SOI films. In the 0.7.mu.m thickness SOI MOSFET, kink effects due to the floating substrate occur and the electron mobility was calculated from the measured g$\_$m/ characteristics, which is about 589cm$\^$2//V.s. The recrystallized SOI films are shown to be a good single crystal silicon.

• Transactions on Electrical and Electronic Materials
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• v.5 no.4
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• pp.129-132
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• 2004

The electrothermal characteristics of a high voltage LIGBT(Lateral Insulated Gate Bipolar Transistor) using thin silicon on insulator (SOI) and silicon on sapphire (SOS) such as thermal conductivity and sink is analyzed by MEDICI. The device simulations demonstrate that the thermal conductivity of the buried oxide is an important parameter for modeling of the thermal behavior of SOI devices. In this paper we simulated the thermal conductivity and temperature distribution of a SOI LIGBT with an insulator layer of SiO$_2$ and $Al_2$O$_3$ at before and after latch-up and verified that the SOI LIGBT with the $Al_2$O$_3$ insulator had good thermal conductivity and reliability.