• Journal of the Microelectronics and Packaging Society
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• v.16 no.4
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• pp.1-4
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• 2009

This work shows how the adoption of a dual-dicing process for silicon wafer separation affects the thermal-cycling reliability (i.e. $-65^{\circ}C$ to $150^{\circ}C$) of the semiconductor devices utilizing lead-on-chip (LOC) die attach technique. In-situ examinations show that conventional single-dicing process directly attacks the edge region of diced devices but dual-dicing process effectively protects the edge region of diced devices from dicing-induced mechanical damage. Probably, this is because the preferential and sacrificial fracture of notched regions induced on the active surface of wafers saves the edge regions. It was also investigated through thermal-cycling tests that the number of thermal-cycling induced failures is much lower at the dual-dicing process than the single-dicing process.

• Journal of IKEEE
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• v.20 no.3
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• pp.279-284
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• 2016

This paper presents a two stage L-band power amplifier realized with a $0.32{\mu}m$ Silicon-On-Insulator (SOI) CMOS technology. To overcome a low breakdown voltage limit of MOSFET, stacked-FET structures are employed, where three transistors in the first stage amplifier and four transistors in the second stage amplifier are connected in series so that their output voltage swings are added in phase. The stacked-FET structures enable the proposed amplifier to achieve a 21.5 dB small-signal gain and 15.7 dBm output 1-dB compression power at 1.9 GHz with a 122 mA DC current from a 4 V supply. The amplifier delivers a 19.7 dBm. This paper presents a two stage L-band power amplifier realized with a $0.32{\mu}m$ Silicon-On-Insulator (SOI) CMOS technology. To overcome a low breakdown voltage limit of MOSFET, stacked-FET structures are employed, where three transistors in the first stage amplifier and four transistors in the second stage amplifier are connected in series so that their output voltage swings are added in phase. The stacked-FET structures enable the proposed amplifier to achieve a 21.5 dB small-signal gain and 15.7 dBm output 1-dB compression power at 1.9 GHz with a 122 mA DC current from a 4 V supply. The amplifier delivers a 19.7 dBm saturated output power with a 16 % maximum Power Added Efficiency (PAE). A bond wire fine tuning technology enables the amplifier a 23.67 dBm saturated output power with a 20.4 % maximum PAE. The die area is $1.9mm{\times}0.6mm$.

• Journal of Technologic Dentistry
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• v.9 no.1
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• pp.67-72
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• 1987

This experimental study presented the study on the dimensional changes of occuring for the denture curing methods. The method is as follows: 1. The master die was made of wax. 2. The Silicon Rubber Mold was made into the same 80 casts. 3. The 80 Wax Plate were made of using the Base Plate Wax. 4. Flasking, Wax-wash, & Resin-packing were performed by the general procedures. 5. The curing method is performed through the four curing methods. (A, B, C, D). Table 2 shows the dimensional change after a day. Table 3 shows the dimensional change after soaking for 30 days in water of the degree of 36 Centigrade. As a result, the A curing method is the most denture curing.

• ETRI Journal
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• v.30 no.6
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• pp.783-789
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• 2008

A bio-inspired vision chip for edge detection was fabricated using 0.35 ${\mu}m$ double-poly four-metal complementary metal-oxide-semiconductor technology. It mimics the edge detection mechanism of a biological retina. This type of vision chip offer several advantages including compact size, high speed, and dense system integration. Low resolution and relatively high power consumption are common limitations of these chips because of their complex circuit structure. We have tried to overcome these problems by rearranging and simplifying their circuits. A vision chip of $160{\times}120$ pixels has been fabricated in $5{\times}5\;mm^2$ silicon die. It shows less than 10 mW of power consumption.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2001.04a
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• pp.45-48
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• 2001

SL(Stereolithogrphy) part is made by piling up thin layers which causes the stair stepping effect at the surface of SL parts. This effect causes excessive surface roughness and requires additional postprocess finishing such as abrasive basting which is detrimental to part geometry and time consuming. Hence paraffin coating and grinding postprocess is proposed to raise the surface quality of SL part. The paraffin which has suitable properties for the proposed postprocess is coated all over the part surface. By grinding the thin layer of coated on the SL part only, the surface roughness can be improved without any damage on the part. From the experimental result, It is verified as very practical for die casting with silicon rubber mold.

• Transactions of the Korean Society of Machine Tool Engineers
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• v.15 no.4
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• pp.39-43
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• 2006

A computer-controlled micro tribotester has been developed to investigate the friction and wear characteristics of thin coatings, which can be applied to silicon-based materials. In the developed system, a step motor gives a reciprocating movement and an electromagnet applies a load between a ball and a plate specimen. Test results confirmed that the application of load in the range of $0.03{\sim}1.8N$ and with a sliding speed of $4.44{\sim}7.70mm/s$ was successfully accomplished. Advantages of the developed micro tribotester are: (1) realization of micro load and displacement applicable to micro electromechanical systems(MEMS) using DC motor and electromagnet (2) continuously variable load and reciprocating speed; and (3) high reliability, which allows for unattended use for long periods.

• Proceedings of the Korean Society of Machine Tool Engineers Conference
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• 1998.03a
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• pp.196-202
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• 1998

Recently, developments in the frontier industry have brought a rapid increase in the use of brittle materials such as silicon wafer, ferrite, sintered carbide, MgO single crystal and die steel. Because of high hardness and brittleness the cracking and chipping are apt to generate in the grinding of brittle materials, but have replaced gradually the high precision grinding. In this study, the optimum system of in-process electrolytic dressing controlled by computer was developed for improving the defects, and could maintain the optimum dressing condition at all times. The control of in-process dressing was simplified using this system, was able to maintain a stable dressing current and was unrelated to the change of dressing condition according to the variation of gap and oxide layer. Therefore, the optimum in-process electrolytic dressing system was constructed and the analysis of grinding mechanism with this system was studied.

• Journal of the Korean Society for Heat Treatment
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• v.11 no.3
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• pp.200-206
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• 1998

The aim of this study is to investigate the effect of impurity level and fabrication processes on the strength, impact and fracture toughness of 7075, 7050 and 7175 aluminum alloy forgings. A specially processed 7175S-T74 aluminum forgings was superior to a conventionally processed 7075-T73, 7050-T74 and 7175-T74 aluminum forgings in both strength and toughness. The reduction of impurity level of iron and silicon has significantly diminished the size and volume fraction of second phase particles such as $Al_7Cu_2Fe$ and $Mg_2Si$. A further reduction of the amount of second phase particles has been observed by applying a special fabrication process. This phenomena result from the application of intermediate soaking at higher temperature and more sufficiant hot working temperature than that of a conventional processing.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.11
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• pp.152-161
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• 1996

This paper descrisbes the implementation of a 20D DCT that can be used for video conference, JPEG, and MPEG-related applications. The implemented DCT consists of two 1-D DCTs and a transposed memory between them, and uses ROM-based multipliers instead of conventional ones. As the system bit length, the minimum bit length that satisfies the accuracy specified by the ITU standard H.261 was chosen through the simulations using the C language. The proposed design uses a dual port RAM for the transposed memory, and processes two bits of input-pixel data simultaneously t ospeed up addition process using two sets of ROMs. The basic system architecture was designed using th Synopsys schematic editor, and internal modules were described in VHDL and synthesized to logic level after simulation. Then, the compass silicon compiler was used to create the final lyout with 0.8um CMOS libraries, using the standard cell approach. The final layout contains about 110, 000 transistors and has a die area of 4.68mm * 4.96mm, and the system has the processing speed of about 50M pixels/sec.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2002.10a
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• pp.808-811
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• 2002

In thixoforming process, the size of Si particles is changed by many parameters of forming. Especially, reheating and heat treatment are very important parameters. It was found that the mechanical properties was significantly improved by the thixoforming process. In this study, to investigate the relation between the mechanical properties and Si particles, the experiment of semi-solid die casting has been performed. Large suspension part with A356 alloy was fabricated with controlled ram speed. The effect of the size and shape of silicon particles on microstructure of tensile test has been investigated.