• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.13 no.2
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• pp.131-136
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• 2000

We have investigated the slurry induced metallic contaminations of undoped and doped silicate oxides surface on CMP cleaning process. The metallic contaminations by CMP slurry were evaluated in four different oxide films, such as plasma enhanced tetra-ethyl-orthyo-silicate glass(PE-TEOS), O3 boro-phos-pho-silicate glass(O3-BPSG), PE-BPSG, and phospho-silicate glass(PSG). All films were polished with KOH-based slurry prior to entering the post-CMP cleaner. The Total X-Ray fluorescence(TXRF) measurements showed that all oxide surfaces are heavily contaminated by potassium and calcium during polishing which is due to a CMP slurry. The polished O3-BPSG films presented higher potassium and calcium contaminations compared to PE-TEOS because of a mobile ions gettering ability of phosphorus. For PSG oxides, the slurry induced mobile ion contamination increased with an increase of phosphorus contents. In addition, the polishing removal rate of PSG oxides had a linear relationship as a function of phosphorus contents.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.8 no.4
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• pp.738-742
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• 2007

The variations in the device characteristics of hydrogenated amorphous thin-film transistors (a-Si:H TFTs) were studied according to the processes of pixel electrode fabrication to make active-matrix flat-panel displays. The off-state current was about 1 pA and the switching ratio was over $10^6$ before fabrication of pixel electrodes; however, the off-state current increased over 10 pA after fabrication of pixel electrodes. Surface treatment on SiNx passivation layers using plasma could improve the off-state characteristics after pixel electrode process. $N_2$ plasma treatment gave the best result. Charge accumulation on the SiNx passivation layer during the deposition of transparent conducting layer might cause the increase of off-state current after the fabrication of pixel electrodes.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.15 no.1
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• pp.61-66
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• 2002

A method for designing antireflection (AR) and antistatic (AS) coating layer by the use of conducting polymer as an electrically conductive transparent layer is proposed. The conducting AR coating is composed of four-layer with alternating high and low refractive index layer: silicon dioxide (n=1.44) and titanium dioxide (n=2.02) prepared at low temperature by sol-gel method are used as the low and high refractive index layer, respectively. The poly(3,4-ethylenedioxythiophene) which has the surface resistivity of 10$^4$Ω/$\square$ is used as a conductive layer. Optical constant of each ARAS coating layers such as refractive index and optical thickness were measured by 7he spectroscopic ellipsometer and from the measured optical constants the spectral properties such as reflectance and transmittance were simulated in the risible region. The reflectance of ARAS films on glass substrate was below 1 %R and the transmittance was higher than 95 % in the visible wavelength (400-700 nm). The measured AR spectral properties was very similar to its simulated results.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2000.07a
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• pp.779-782
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• 2000

Silicone rubbers are first silicone polymers and has named silicone from existence of Si-O bond similar to Keton. Silicon in organic compound has been called silicone, and linear or network polymers. Silicone rubbers have been used as an power insulator because they are well weather proof, ozone proof and have excellent electric characteristics, thermal stability, cold resistance and low surface energy. Especially, it is known that they have very excellent characteristics at 200[$^{\circ}C$]. For this study, we made silicone rubbers as specimens and we measured dielectric loss tangent due to applied voltage at temperature range 25[$^{\circ}C$] to 180[$^{\circ}C$] and frequency range 20[Hz] to 1${\times}$10$\^$6/[Hz] to examine dielectric properties. We measured dielectric loss tangent to study the insulation performance of silicone rubbers.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.06a
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• pp.110-111
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• 2006

이중 에피층을 가지는 SOI (Silicon-On-Insulator) RESURF(REduced SURface Field) LIGBT(Lateral Insulated Gate Bipolar Transistor) 소자의 에피층 두께에 따른 항복전압 특성을 분석하였다. 이중 에 피층 구조를 가지는 SOI RESURF LIGBT 소자는 전하보상효과를 얻기 위해 기존 LIGBT 소자의 n 에피로 된 영역을 n/p 에피층의 이중 구조로 변경한 소자로 n/p 에피층 영역내의 전하간 상호작용에 의해 에피 영역 전체가 공핍됨으로써 높은 에피 영역농도에서도 높은 항복전압을 얻을 수 있는 소자이다. 본 논문에서는 LIGBT 에피층의 전체 두께와 농도를 고정한 상태에서 n/p 에피층의 두께가 변하는 경우에 항복전압 특성의 변화에 대해 simulation을 통해 분석하였다.

• Korean Journal of Optics and Photonics
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• v.7 no.2
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• pp.101-111
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• 1996

Optical microscopes integrated with CCD cameras are widely used for automatic inspection of precision circuit patterns fabricated on glass masks and silicon wafers. For this application it is important to position the object always is focus so that the image appears in good quality while the microscope scans the object. However, as the magnification of the microscope is taken large for fine resolution the depth of focus becomes small, often in submicron ranges, requiring special care in focusing. This study proposes a new auto-focusing method, which can be readily incorporated in existing optical configuration of microscope. This method is based on optical triangulation using a separate beam of laser and two photodiodes, eliminating focus errors caused by surface roughness and waviness. Experimental results prove that the method can produce focus error signals which are very sensitive with a resolution of 5 nm within 0.5 ${\mu}{\textrm}{m}$ accuracy.

• Proceedings of the Korean Society of Tribologists and Lubrication Engineers Conference
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• 2000.11a
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• pp.406-413
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• 2000

The friction and wear behaviors of Magnetron Sputtered MoS$_2$films were investigated by using a pin on disk type tester which was designed and manufactured for this experiment. The experiment was conducted by using silicon nitride (Si$_3$N$_4$) as a pin material and Magnetron Sputtered MoS$_2$on bearing steel (STB2) as a disk material, under operating conditions that include different surface roughness (Polishing specimen, Grinding specimen)(2types), linear sliding velocities in the range of 22, 44, 66mm/sec (3types), normal loads vary from 9.8N, 19.6N, 29.4N(3types), corresponding to contact pressures of 1.9∼2.7GPa and atmospheric conditions of high vacuum( 1.3${\times}$10$\^$-4/Pa), medium vacuum( 1.3${\times}$10$\^$-l/Pa), ambient air(10$\^$5/Pa)(3types). We investigated fracture mechanism in magnetron sputtered MoS$_2$films with Magnetron Sputtering method in each experiment.

• Proceedings of the Korean Society for Technology of Plasticity Conference
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• 2005.09a
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• pp.193-197
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• 2005

This paper presents a method by which multiple holes of ultra small size can be punched simultaneously. Silicon wafers were used to fabricate punching die. Workpiece used in the present investigation were the rolled pure copper of $3{\mu}m$ in thickness and CP titanium of $1.5{\mu}m$ in thickness. The metal foils were punched with the dies and arrays of circular and rectangular holes were made. The diameter of holes ranges from $2-10{\mu}m$. The process set-up is similar to that of the flexible rubber pad forming or Guerin process. Arrays of holes were punched successfully in one step forming. The punched holes were examined in terms of their dimensions, surface qualities, and potential defect. The effects of the die hole dimension on ultra small size hole formation of the thin foil were discussed. The optimum process condition such as proper die shape and diameter-thickness ratio (d/t) were also discussed. The results in this paper show that the present method can be successfully applied to the fabrication of ultra small size hole array in a one step operation.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.02a
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• pp.405-405
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• 2010

Thermocouple 을 통해 Inductively coupled plasma 에 노출된 실리콘 기판 표면온도를 공정조건 변화 에 따라 실시간 (in-situ) 측정하였다. 이를 바탕으로 공정변화에 따른 플라즈마 내 활성종의 거동을 연구하였다. 더 나아가 기판의 표면온도변화 및 활성종의 거동해석을 토대로 공정변화에 의한 딥 실리콘 구조형성 메커니즘을 해석하였다. 플라즈마에 노출된 기판표면 온도를 상승시키는 주 활성종은 positive ion 이며 ICP power, Bias power, 플라즈마 압력 변화에 따라 positive ion 의 밀도 및 가속에너지가 변화하는데 이러한 거동변화는 기판의 표면온도를 변화시킴을 알 수 있었다. 딥 실리콘 구조의 측벽 및 바닥에 형성되어 있는 passivaiton layer 즉 $SiO_xF_y$(silicon oxyflouride) 는 온도에 매우 민감한 물질이며 이는 딥 실리콘 구조 내부로 입사하는 positive ion 거동변화에 따라 그 성질이 변화하여 deep Si 구조 형상을 변화시킴을 알 수 있었다. 기판표면 온도가 $0^{\circ}C$ 이하의 극저온으로 유지된 상황에서 플라즈마를 방전할 경우 positive ions 의 가속에너지로 인해 기판표면온도가 상승하며 액화질소 유량증가를 통해 다시 기판의 표면온도를 유지시킬 수 있었다. 이를 통해 플라즈마 방전 전과 방전 후의 기판 표면온도는 상온의 기판뿐만 아니라 극저온의 기판에서도 다름을 알 수 있었다. 냉각환경 변화에 따른 딥 실리콘 구조형성 메커니즘을 positive ions 거동 그리고 온도 감소에 의한 $SiO_xF_y$ 성질 변화를 이용해 해석할 수 있었다.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.08a
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• pp.90.2-90.2
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• 2013

Vertically-aligned silicon nanostructure arrays (SNAs) have been drawing much attention due to their useful electrical properties, large surface area, and quantum confinement effect. SNAs are typically fabricated by chemical vapor deposition, reactive ion etching, or wet chemical etching. Recently, metal-assisted chemical etching process, which is relatively simple and cost-effective, in combination with nanosphere lithography was recently demonstrated for vertical SNA fabrication with controlled SNA diameters, lengths, and densities. However, this method exhibits limitations in terms of large-area preparation of unperiodic nanostructures and SNA geometry tuning independent of inter-structure separation. In this work, we introduced the layerby- layer deposition of polyelectrolytes for holding uniformly dispersed polystyrene beads as mask and demonstrated the fabrication of well-dispersed vertical SNAs with controlled geometric parameters on large substrates. Additionally, we present a new means of building in vitro neuronal networks using vertical nanowire arrays. Primary culture of rat hippocampal neurons were deposited on the bare and conducting polymer-coated SNAs and maintained for several weeks while their viability remains for several weeks. Combined with the recently-developed transfection method via nanowire internalization, the patterned vertical nanostructures will contribute to understanding how synaptic connectivity and site-specific perturbation will affect global neuronal network function in an extant in vitro neuronal circuit.