• 대한의용생체공학회:학술대회논문집
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• 대한의용생체공학회 1998년도 추계학술대회
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• pp.147-148
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• 1998

In this paper, we developed the process for depth-probe type silicon microelectrode arrays. The process consists of four mask steps only. The steps are for defining sites, windows, and for shaping probe using plasma etch from above, and for shaping using wet etch from below, respectively. The probe thickness is controlled by dry etching, not by impurity diffusion. We used gold electrodes with a triple dielectric system consisting of oxide/nitride/oxide. The shank of the probe taper from 200um to tens of urn tip and has 30 um thickness.

• Bulletin of the Korean Chemical Society
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• 제33권1호
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• pp.83-89
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• 2012

Due to the potential importance and usefulness, usage of highly ordered nanoporous anodized aluminum oxide can be broadened in industry, when highly ordered anodized aluminum oxide can be placed on a substrate with controlled thickness. Here we report a facile route to highly ordered nanoporous alumina with the thickness of hundreds-of-nanometer on a silicon wafer substrate. Hexagonally or tetragonally ordered nanoporous alumina could be prepared by way of thermal imprinting, dry etching, and anodization. Adoption of reusable polymer soft molds enabled the control of the thickness of the highly ordered porous alumina. It also increased reproducibility of imprinting process and reduced the expense for mold production and pattern generation. As nanoporous alumina templates are mechanically and thermally stable, we expect that the simple and costeffective fabrication through our method would be highly applicable in electronics industry.

• Journal of Electrical Engineering and information Science
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• 제2권6호
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• pp.212-216
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• 1997

A new metal tip fabrication process for low voltage operation is reported in this paper. The key element of the fabrication process is that isotropic silicon etching and oxidation process used in silicon tip fabrication is utilized for gate hole size reduction and gate oxide layer. A metal FEA with 625 tips was fabricated in order to demonstrate the validity of the new process and submicron gate apertures were successfully obtained from originally 1.7$\mu\textrm{m}$ diameter mask. The emission current above noise level was observed at the gate bias of 50V. The required gate voltage to obtain the anode current of 0.1${\mu}\textrm{A}$/tip was 74V and the emission current was stable above 2${\mu}\textrm{A}$/tip without any disruption. The local field conversion factor and the emitting area were calculated as 7.981${\times}$10\ulcornercm\ulcorner and 3.2${\times}$10\ulcorner$\textrm{cm}^2$/tip, respectively.

• 한국세라믹학회지
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• 제34권10호
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• pp.1021-1026
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• 1997

RuO2 thin film has reasonably good conductivity and stiffness and it is thought to substitute for the cantilever beam made up of Pt and Si3N4 double layers in microactuators. Therefore, anisotopic Si etching was performed using RuO2 thin film as a mask layer in 25 wt. % TMAH water solution. In the etching temperature ranging from 6$0^{\circ}C$ to 75$^{\circ}C$, the etch rates of all the crystallographic directions increased linearly as the etching temperature increased. The etch rate ratio(selectivity) of [111]/[100] which varied from 0.08 to 0.14, was not sensitive to temperature. The activation energies for [110] direction, [100] direction and [111] direction were 0.50, 0.66 and 1.04eV, respectively. RuO2 cantilever beam with a clean surface was formed at the etching temperatures of 6$0^{\circ}C$ and $65^{\circ}C$. But the damages due to formation of pin holes on RuO2 surface were observed beyond 7$0^{\circ}C$. The tensile stress of RuO2 thin films caused the cantilever bending upward. As a result, it was demonstrated that the formation of conducting oxide RuO2 cantilever beam which can replace the role of an electrode and supporting layer could be possible by TMAH solution.

• 마이크로전자및패키징학회지
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• 제19권1호
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• pp.39-45
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• 2012

Cu-Cu 패턴의 직접접합 공정을 위하여 Buffered Oxide Etch(BOE) 및 Hydrofluoric acid(HF)의 습식 조건에 따른 Cu와 $SiO_2$의 식각 특성에 대한 평가를 수행하였다. 접촉식 3차원측정기(3D-Profiler)를 이용하여 Cu와 $SiO_2$의 단차 및 Chemical Mechanical Polishing(CMP)에 의한 Cu의 dishing된 정도를 분석 하였다. 실험 결과 BOE 및 HF 습식 식각 시간이 증가함에 따라 단차가 증가 하였고, BOE가 HF보다 더 식각 속도가 빠른 것을 확인하였다. BOE 및 HF 습식 식각 후 Cu의 dishing도 식각시간 증가에 따라 감소하였다. 식각 후 산화막 유무를 알아보기 위해 Cu표면을 X-선 광전자 분광법(X-ray Photoelectron Spectroscopy, XPS)를 이용하여 분석 한 결과 HF습식 식각 후 BOE습식 식각보다 Cu표면산화막이 상대적으로 더 얇아 진 것을 확인하였다.

• Journal of the Optical Society of Korea
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• 제20권2호
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• pp.291-299
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• 2016

We have investigated the ultimate limits of nonuniform grating couplers (NGCs) for optimized fiber coupling to silicon waveguides, compared to uniform grating couplers (UGCs). Simple grating coupler schemes, which can be fabricated in etching steps of the conventional complementary metal-oxide semiconductor (CMOS) process on silicon-on-insulator (SOI) wafers without forming any additional overlay structure, have been simulated numerically and demonstrated experimentally. Optimum values of the grating period, fill factor, and groove number for ultimate coupling efficiency of the NGCs are determined from finite-difference time-domain (FDTD) simulation, and confirmed with experimentally demonstrated devices by comparison to those for the UGCs. Our simulated results indicate that maximum coupling efficiency of NGCs is possible when the minimum pattern size is below 50 nm, but the experimental value for the maximum coupling efficiency is limited by the attainable fabrication tolerance in a practical device process.

• Transactions on Electrical and Electronic Materials
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• 제1권1호
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• pp.6-11
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• 2000

The hydrogen plasma treatment of silicon wafers in the reactive ion-etching mode was studied for the application to silicon-on-insulator wafers which were prepared using the wafer bonding technique. The chemical reactions of hydrogen plasma with surface were used for both surface activation and removal of surface contaminants. As a result of exposure of silicon wafers to the plasma, an active oxide layer was found on the surface. This layer was rendered hydrophilic. The surface roughness and morphology were examined as functions of the plasma exposing time and power. In addition, the surface became smoother with the shorter plasma exposing time and power. The value of initial surface energy estimated by the crack propagation method was 506 mJ/㎡, which was up to about three times higher as compared to the case of conventional direct using the wet RCA cleaning method.

• 한국정밀공학회지
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• 제23권7호
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• pp.138-145
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• 2006

A nanopatterning technique was proposed and demonstrated for low cost and mass productive process using the scanning probe lithography (SPL) and soft lithography. The nanometer scale structure is fabricated by the localized generation of oxide patterning on the H-passivated (100) silicon wafer, and soft lithography was performed to replicate of nanometer scale structures. Both height and width of the silicon oxidation is linear with the applied voltagein SPL, but the growth of width is more sensitive than that of height. The structure below 100 nm was fabricated using HF treatment. To overcome the structure height limitation, aqueous KOH orientation-dependent etching was performed on the H-passivated (100) silicon wafer. Soft lithography is also performed for the master replication process. Elastomeric stamp is fabricated by the replica molding technique with ultrasonic vibration. We showed that the elastomeric stamp with the depth of 60 nm and the width of 428 nm was acquired using the original master by SPL process.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1999년도 하계학술대회 논문집 G
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• pp.3310-3312
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• 1999

We have studied the method of silicon direct bonding using the mixture of $HNO_$, $H_2O_2$, and HF chemicals called the controlled slight etch (CSE) solution for the effective wafer cleaning. CSE, two combinations of oxidizing and etching agents, have been used to clean the silicon surfaces prior to wafer bonding. Two wafers of silicon and silicon dioxide were contacted each other at room temperature and postannealed at $300{\sim}1100^{\circ}C$ in $N_2$ ambient for 2.5 h. We have cleaned silicon wafers with the various HF concentrations and characterized the parameters with regard to surface roughness, chemical nature, chemical oxide thickness, and bonding energy. It was observed that the chemical oxide thickness on silicon wafer decreased with increasing HF concentrations. The initial interfacial energy and final energy postannealed at $1100^{\circ}C$ for 2.5h measured by the crack propagation method was 122 $mJ/m^2$ and 2.96 $mJ/m^2$, respectively.

• 한국전기전자재료학회논문지
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• 제14권1호
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• pp.1-5
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• 2001

STI(shallow trench isolation)-CMP(chemical mechanical polishing) process have been substituted for LOCOS(local oxidation of silicon) process to obtain global planarization in the below sub-0.5㎛ technology. However TI-CMP process, especially TI-CMP with RIE(reactive ion etching) etch back process, has some kinds of defect like nitride residue, torn oxide defect, etc. In this paper, we studied how to reduced torn oxide defects after STI-CMP with RIE etch back processed. Although torn oxide defects which can occur on trench area is not deep and not severe, torn oxide defects on moat area is not deep and not severe, torn oxide defects on moat area is sometimes very deep and makes the yield loss. Thus, we did test on pattern wafers which go through trench process, APECVD process, and RIE etch back process by using an IPEC 472 polisher, IC1000/SUVA4 PAD and KOH base slurry to reduce the number of torn defects and to study what is the origin of torn oxide defects.