• 전자통신동향분석
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• 제36권3호
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• pp.23-33
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• 2021

Two main technologies of III-V/Si laser diode for optical communication, direct epitaxial growth, and wafer bonding were studied. Until now, the wafer bonding has been vigorously studied and seems promising for the ideal III-V/Si laser. However, the wafer bonding process is still complicated and has a limit of mass production. The development of a concise and innovative integration method for silicon photonics is urgent. In the future, the demand for high-speed data processing and energy saving, as well as ultra-high density integration, will increase. Therefore, the study for the hetero-junction, which is that the III-V compound semiconductor is directly grown on Si semiconductor can overcome the current limitations and may be the goal for the ideal III-V/Si laser diode.

• 한국정밀공학회지
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• 제29권5호
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• pp.563-571
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• 2012

In 3D integration package using TSV technology, bonding is the core technology for stacking and interconnecting the chips or wafers. During bonding process, however, warpage and high stress are introduced, and will lead to the misalignment problem between two chips being bonded and failure of the chips. In this paper, a finite element approach is used to predict the warpages and stresses during the bonding process. In particular, in-plane deformation which directly affects the bonding misalignment is closely analyzed. Three types of bonding technology, which are Sn-Ag solder bonding, Cu-Cu direct bonding and SiO2 direct bonding, are compared. Numerical analysis indicates that warpage and stress are accumulated and become larger for each bonding step. In-plane deformation is much larger than out-of-plane deformation during bonding process. Cu-Cu bonding shows the largest warpage, while SiO2 direct bonding shows the smallest warpage. For stress, Sn-Ag solder bonding shows the largest stress, while Cu-Cu bonding shows the smallest. The stress is mainly concentrated at the interface between the via hole and silicon chip or via hole and bonding area. Misalignment induced during Cu-Cu and Sn-Ag solder bonding is equal to or larger than the size of via diameter, therefore should be reduced by lowering bonding temperature and proper selection of package materials.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1996년도 하계학술대회 논문집 C
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• pp.1943-1945
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• 1996

In this paper, we developed a modified direct bonding method for the application of vacuum devices. By the proposed method, we successfully bonded the following materials: Si-Si, Si-$SiO_2$-Si, glass-Si, and glass-$SiO_2$-Si. In our experiments, we used corning #7070 wafer type glass and (100) or (110) single crystalline silicon wafers. In order to enhance the initial bonding strength we contacted the materials to be bonded as D. I. water wetted on the surfaces and evaporated the water under the room temperature and atmosphere environment. Finally we realized the glass bonding by simple direct bonding method which has been performed by electrostatic bonding method until now.

• 한국세라믹학회:학술대회논문집
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• 한국세라믹학회 2000년도 춘계총회,특별강연,심포지움,연구발표회
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• pp.127.1-127.1
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• 2000

• 대한전기학회:학술대회논문집
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• 대한전기학회 1996년도 하계학술대회 논문집 C
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• pp.1988-1990
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• 1996

In this work, we have grown or evaporated thermal oxide and E-beam oxide on the (100) oriented n-type silicon wafers, respectively and they were directly bonded with another silicon wafer after hydrophilization using solutions of three types of $HNO_3$, $H_{2}SO_{4}$ and $NH_{4}OH$. Changes of average surface roughness after hydrophilizations of the single crystalline silicon wafer, thermal oxide and E-beam evaporated silicon oxide were studied using atomic force microscope. Bonding interfaces of the bonded pairs were inspected using scanning electron microscope. Void and non-contact area of the bonded pairs were also inspected using infrared transmission microscope.

• 한국재료학회지
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• 제14권5호
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• pp.315-321
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• 2004

The void evolution in direct bonding process of $Si/Si_3$$N_4$ ∥ $SiO_2$/Si silicon wafer pairs has been investigated with an infrared camera. The voids that formed in the premating process grew in the conventional furnace annealing process at a temperature of $600^{\circ}C$. The voids are never shrunken even with the additional annealing process at the higher temperatures. We observed that the voids became smaller and disappeared with sequential scanning by our newly proposed fast linear annealing(FLA). FLA irradiates the focused line-shape halogen light on the surface while wafer moves from one edge to the other. We also propose the void shrinking mechanism in FLA with the finite differential method (FDM). Our results imply that we may eliminate the voids and enhance the yield for the direct bonding of wafer pairs by employing FLA.

• 한국표면공학회:학술대회논문집
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• 한국표면공학회 2018년도 춘계학술대회 논문집
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• pp.102-102
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• 2018

Electronic industry had required the finer size and the higher performance of the device. Therefore, 3-D die stacking technology such as TSV (through silicon via) and micro-bump had been used. Moreover, by the development of the 3-D die stacking technology, 3-D structure such as chip to chip (c2c) and chip to wafer (c2w) had become practicable. These technologies led to the appearance of HBM (high bandwidth memory). HBM was type of the memory, which is composed of several stacked layers of the memory chips. Each memory chips were connected by TSV and micro-bump. Thus, HBM had lower RC delay and higher performance of data processing than the conventional memory. Moreover, due to the development of the IT industry such as, AI (artificial intelligence), IOT (internet of things), and VR (virtual reality), the lower pitch size and the higher density were required to micro-electronics. Particularly, to obtain the fine pitch, some of the method such as copper pillar, nickel diffusion barrier, and tin-silver or tin-silver-copper based bump had been utillized. TCB (thermal compression bonding) and reflow process (thermal aging) were conventional method to bond between tin-silver or tin-silver-copper caps in the temperature range of 200 to 300 degrees. However, because of tin overflow which caused by higher operating temperature than melting point of Tin ($232^{\circ}C$), there would be the danger of bump bridge failure in fine-pitch bonding. Furthermore, regulating the phase of IMC (intermetallic compound) which was located between nickel diffusion barrier and bump, had a lot of problems. For example, an excess of kirkendall void which provides site of brittle fracture occurs at IMC layer after reflow process. The essential solution to reduce the difficulty of bump bonding process is copper to copper direct bonding below $300^{\circ}C$. In this study, in order to improve the problem of bump bonding process, copper to copper direct bonding was performed below $300^{\circ}C$. The driving force of bonding was the self-annealing properties of electrodeposited Cu with high defect density. The self-annealing property originated in high defect density and non-equilibrium grain boundaries at the triple junction. The electrodeposited Cu at high current density and low bath temperature was fabricated by electroplating on copper deposited silicon wafer. The copper-copper bonding experiments was conducted using thermal pressing machine. The condition of investigation such as thermal parameter and pressure parameter were varied to acquire proper bonded specimens. The bonded interface was characterized by SEM (scanning electron microscope) and OM (optical microscope). The density of grain boundary and defects were examined by TEM (transmission electron microscopy).

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2003년도 하계학술대회 논문집 Vol.4 No.1
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• pp.147-150
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• 2003

In this paper, We fabricated a high temperature pressure sensor using SBD(silicon- direct-bonding) wafer of $Si/SiO_2$/Si-sub structure. This sensor was very sensitive because the piezoresistor is fabricated by single crystal silicon of the first layer of SDB wafer. Also, it was possible to operate the sensor at high temperature over $120^{\circ}C$ which is the temperature limitation of general silicon sensor because the piezoresistor was dielectric isolation from silicon substrate using silicon dioxide of the second layer. The sensitivity of this sensor is very high as the measured result of D2200 shows $183.6\;{\mu}V/V{\cdot}kPa$. Also, the output characteristic of linearity was very good. This sensor was available at high temperature as $300^{\circ}C$.

• 센서학회지
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• 제13권3호
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• pp.175-181
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• 2004

A pressure sensor for high temperature was fabricated by using a SDB(Silicon-Direct-Bonding) wafer with a Si/$SiO_{2}$/ Si structure. High pressure sensitivity was shown from the sensor using a single crystal silicon of the first layer as a piezoresistive layer. It also was made feasible to use under the high temperature as of over $120^{\circ}C$, which is generally known as the critical temperature for the general silicon sensor, by isolating the piezoresistive layer dielectrically and thermally from the silicon substrate with a silicon dioxide layer of the second layer. The pressure sensor fabricated in this research showed very high sensitivity as of $183.6{\mu}V/V{\cdot}kPa$, and its characteristics also showed an excellent linearity with low hysteresis. This sensor was usable up to the high temperature range of $300^{\circ}C$.

• 센서학회지
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• 제3권3호
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• pp.45-53
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• 1994

실리콘의 직접 접합 방법과 2단계 전기화학적 식 정지 방법을 이용하여 새로운 구조의 실리콘 다이아프램을 제조하였다. 이러한 다이아프램 구조를 기계량 센서에 이용하면 공동의 깊이와 다이아프램의 두께를 보다 정교하게 조절할 수 있다. 또한, 접합 계면에서 발생하는 응력이 다이아프램의 표면으로 전달되는 것을 피할 수 있다. 최종적으로, 제조된 다이아프램을 이용하여 암저항형 실리콘 압력 센서를 제작하였고 압력 단위의 표시가 가능한 디지탈 압력 측정기를 구현하였다.