• Proceedings of the Korean Society of Precision Engineering Conference
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• 한국정밀공학회 1994년도 추계학술대회 논문집
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• pp.670-675
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• 1994

Yhis paper describes a fault diagnosis simulation of the Real-Time Multiple Fault Dignosis System (RTMFDS) for forcasting faults in a system and deciding current machine state from signal information. Comparing with other diagnosis system for single fault,the system developed deals with multiple fault diagnosis,comprising two main parts. One is a remotesignal generating and transimission terminal and the other is a host system for fault diagnosis. Signal generator generate the random fault signal and the image information, and send this information to host. Host consists of various modules and agents such as Signal Processing Module(SPM) for sinal preprocessing, Performence Monotoring Module(PMM) for subsystem performance monitoring, Trigger Module(TM) for multi-triggering subsystem fault diagnosis, Subsystem Fault Diagnosis Agent(SFDA) for receiving trigger signal, formulating subsystem fault D\ulcornerB and initiating diagnosis, Fault Diagnosis Module(FDM) for simulating component fault with Hierarchical Artificial Neural Network (HANN), numerical models and Hofield network,Result Agent(RA) for receiving simulation result and sending to Treatment solver and Graphic Agent(GA). Each agent represents a separate process in UNIX operating system, information exchange and cooperation between agents was doen by IPC(Inter Process Communication : message queue, semaphore, signal, pipe). Numerical models are used to deseribe structure, function and behavior of total system, subsystems and their components. Hierarchical data structure for diagnosing the fault system is implemented by HANN. Signal generation and transmittion was performed on PC. As a host, SUN workstation with X-Windows(Motif)is used for graphic representation.

• Journal of Korea Society of Industrial Information Systems
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• 제7권2호
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• pp.74-81
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• 2002

In general, a multipath generator consists of a time delay generator, phase rotator, and amplitude attenuator, and is implemented mostly in an analog manner. Analog, or partially analog versions of a multipath generator is disadvantageous in that they may suffer from problems associated with component aging and adjustment, signal fidelity degradation stemming from repeated A/D and D/A conversion use of high frequency to achieve fine i.e., subsample fractional tin delays. This paper presents the design and implementation methodology of a full digital multipath generator which can be used in performance evaluations of digital terrestrial television as well as communications, receivers. In particular, an efficient practical method is proposed which can achieve both integer and fractional time delays simultaneously, without placing restrictions on the allowable system master clock frequency. The proposed algorithm lends itself to minimizing hardware implementation cost by relegating some fixed put of the computation involved to an IBM PC. The proposed multipath generator occupies only a single digital board space, and its experimental results are provided to corroborate the proposed implementation methodology.

• Journal of the Korean Society for Nondestructive Testing
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• 제29권2호
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• pp.137-144
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• 2009

In this paper, the signal analysis of eddy current array probe was performed to analyze the electromagnetic characteristics with the variation of FBH(flat bottomed hole) defects size on steam generator tube in NPP(nuclear power plants) using the electromagnetic finite element method. To obtain the electromagnetic characteristic of probes, the governing equation was derived from Maxwell's equations, and the individual problem was analyzed by using the 3-dimensional finite element method. For the simulation FBH defects were used. The depth of FBH defects were 20%, 40%, 60%, 80% and 100% of steam generator(SG) tube thickness, and it was assumed that the defects were located on the tube outside. And the operation frequencies of 100 kHz, 300 kHz and 400 kHz were used. Material of specimen was Inconel 600 which is usually used for SG tubes in NPP. The signal difference could be observed according to the size variation of depth of FBH defects and operation frequencies. The results in this paper can be helpful when the ECT(eddy current testing) signals from EC array probe are evaluated and analyzed.

• Journal of IKEEE
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• 제15권1호
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• pp.23-28
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• 2011

This paper describes design and implementation of a spread spectrum clock generator(SSCG). The proposed architecture generates the spread spectrum clock controlling a input voltage signal for VCDL(Voltage Controlled Delay Line). Spread charge pump is controlled by the SSC modulation logic block provides a control signal to VCDL through LPF in DLL. By using this architecture, chip area and power consumption can be reduced because it is not necessary additional circuit to control modulation rate. This circuit has been designed and fabricated using the UMC 0.25um CMOS technology. The chip occupies an area of 290${\times}$120um^2.

• Proceedings of the Korean Society for Noise and Vibration Engineering Conference
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• 한국소음진동공학회 2007년도 추계학술대회논문집
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• pp.1037-1041
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• 2007

With the advent of sound field simulator, many sound fields have been reproduced by obtaining the impulse responses of specific acoustic spaces like famous concert hall, opera house. This sound field reproduction has been done by the linear convolution operation between the sound input signal and the impulse response of certain acoustic space. However, the conventional finite impulse response based linear convolution operation always makes real-time implementation of sound field generator impossible due to the large amount of computational burden. This paper introduces the fast convolution method using perceptual redundancy in the processed signals, input audio signal and room impulse response. Temporal and spectral psycho-acoustic filters considering masking effects are implemented in the proposed convolution structure. It reduces the computational burden of convolution methods for realtime implementation of a sound field generator. The conventional convolutions are compared with the proposed one in views of computational burden and sound quality. In the proposed method, a considerable reduction in the computational burden was realized with acceptable changes in sound quality.

• Journal of the Institute of Electronics Engineers of Korea CI
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• 제40권5호
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• pp.298-305
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• 2003

This paper describes a 128-channel hardware simulator that is useful for verification and testing of digital circuits. It performs logic analyzer function and signal generator function at the same time. The core module, which implements one channel of the simulator, operates as a controller with independent memory and internal mode. Therefore, we can easily extend the number of channels with addition of core module. Moreover, since the simulator was implemented as a PC based system, one can construct a low-cost system and can configure convenient GUI(Graphic User Interface) environment. The simulator implemented using FPGA operates at 50Mhz and consumes 55W power as average.

• Transactions of the Korean Society for Noise and Vibration Engineering
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• 제18권2호
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• pp.231-237
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• 2008

With the advent of sound field simulator, many sound fields have been reproduced by obtaining the impulse responses of specific acoustic spaces like famous concert hall, opera house. This sound field reproduction has been done by the linear convolution operation between the sound input signal and the impulse response of certain acoustic space. However, the conventional finite impulse response based linear convolution operation always makes real-time implementation of sound field generator impossible due to the large amount of computational burden. This paper introduces the fast convolution method using perceptual redundancy in the processed signals, input audio signal and room impulse response. Temporal and spectral real-time masking blocks are implemented in the proposed convolution structure. It reduces the computational burden of convolution methods for real-time implementation of a sound field generator. The conventional convolutions are compared with the proposed one in views of computational burden and sound quality. In the proposed method, a considerable reduction in the computational burden was realized with acceptable changes in sound quality.

• Journal of the Institute of Convergence Signal Processing
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• 제11권3호
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• pp.226-231
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• 2010

This paper proposes a new coding technique for constructing error correcting high rate DC-free multimode code using a generator matrix generated from a sparse parity-check matrix. The scheme exploits high rate generator matrixes for producing distinct candidate codewords. The decoding complexity depends on whether the syndrome of the received codeword is zero or not. If the syndrome is zero, the decoding is simply performed by expurgating the redundant bits of the received codeword. Otherwise, the decoding is performed by a sum-product algorithm. The performance of the proposed scheme can achieve a reasonable DC-suppression and a low bit error rate.

• The Journal of Korean Institute of Communications and Information Sciences
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• 제11권1호
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• pp.73-84
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• 1986

A statistical method is proposed which estimates an edge that is one of the basic features in image understanding. The conventional edge detection techniques are performed well for a deterministic singnal, but are not satisfactory for a statistical signal. In this paper, we use the likelihood function which takes account of the statistical property of a signal, and derive the decision function from it. We propose the maximum likelihood edge detection technique which estimates an edge point which maximizes the decision function mentioned above. We apply this technique to statistecal signals which are generated by using the random number generator. Simnulations show that the statistical edge detection technique gives satisfactory results. This technique is extended to the two-dimensional image and edges are found with a good accuracy.

• The Bulletin of The Korean Astronomical Society
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• 제37권2호
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• pp.228.1-228.1
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• 2012

Digital waveform generation technology for SAR payload can be divided into DDS(Direct Digital Synthesizer) method and Memory Mapped(M/M) method. DDS is the single chip which consists of the Sine Table, NCO(Numerically Controlled Oscillator), DAC, and so on. DDS method is a very simple method because the circuit configuration is not complex but has a disadvantage that can not control phase and amplitude easily by using NCO. M/M method has the complexity of the circuit configuration because it requires the memories which stores the waveforms, the control circuits, and DAC. And this method should apply the high interface technology for being compatible with the wide bandwidth of the digital signal and has the difficulty for PCB design because the number of the signal lines should be increased according to the number of the data bits for DAC. Although it has several disadvantages, this method has the capability of pre-distortion function which can compensate the phase and amplitude characteristics of the system and also has an excellent advantage to make any arbitrary waveform, so this method is considered as an important technology with DDS method. This research describes the technological trends of the waveform generator for the SAR payload and analyzes the characteristics of the technology.