• 한국재료학회지
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• 제8권2호
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• pp.165-172
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• 1998

초고진공에서 in situ 고상 에피택셜 방법으로 Si(111)기판 위에 에피택셜 $CoSi_2$ 초박막과 $Si/epi-CoSi_2/Si$(111) 의 이중 이종에피택셜 구조를 성장 시켰다. 2-MeV $^4He^{++}$ 이온 후방산란 분광기와 X-선 회절분석기 및 고분해능 투과전자 현미경을 이용하여 성장된 $CoSi_2$와 $Si/epi-CoSi_2/Si$(111)의 상, 조성, 결정성 그리고 계면의 미세구조를 조사하였다. 실온에서 증착된 Co 박막은 texture 구조를 갖는 Stransky-Krastanov 성장 모드를 나타내었다. 실온에서 Si(111)-$7\times{7}$ 기판 위에 Co를 $50\AA$ 증착한 후 $700^{\circ}C$로 10분간 in situ 열처리했을 때 초박막 A-type $CoSi_2$상이 성장되었고, 정합상관계는 $CoSi_2$[110]//Si[110] and $CoSi_2$(002)//Si(002)였으며, 편의각은 없었다. A-type $CoSi_2$/Si(111)계면은 평활하고 coherent 하였다. 양질의 epi-Si/epi-$CoSi_2$(A-type)/Si(111)구조는 Co/Si(111)계를 $700^{\circ}C$로 10분간 in situ로 열처리한 후 기판을 $500^{\circ}C$로 유지하면서 Si을 증착하였을 때 형성되었다.

• 대한전기학회논문지:전기물성ㆍ응용부문C
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• 제49권1호
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• pp.24-29
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• 2000

We propose a simple method to control the crystallization depth of amorphous silicon (a-Si) deposited by PECVD or LPCVD during the excimer laser annealing (ELA). Employing the new method, we have formed poly-Si/a-Si double film and fabricated a new poly-Si TFT with vertical a-Si offsets between the poly-Si channel and the source/drain of TFT without any additional photo-lithography process. The maximum leakage current of the new poly-Si TFT decreased about 80% due to the highly resistive vertical a-Si offsets which reduce the peak electric field in drain depletion region and suppress electron-hole pair generation. In ON state, current flows spreading down through broad a-Si cross-section in the vertical a-Si offsets and the current density in the drain depletion region where large electric field is applied is reduced. The stability of poly-Si TFT has been improved noticeably by suppressing trap state generation in drain region which is caused by high current density and large electric field. For example, ON current of the new TFT decreased only 7% at a stress condition where ON current of conventional TFT decreased 89%.

• 한국해양공학회:학술대회논문집
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• 한국해양공학회 2006년 창립20주년기념 정기학술대회 및 국제워크샵
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• pp.158-161
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• 2006

SiC materials have been extensively studied for high temperature components in advanced energy conversion system and advanced gas turbine. However, the brittle characteristics of SiC such as law fracture toughness and law strain-to fracture impose a severe limitation on the practical applications of SiC materials. SiC/SiC composites can be considered as a promising candidate in various structural materials, because of their good fracture toughness. In this composite system, the direction of SiC fiber will give an effect to the mechanical properties. It is therefore important to control a properdirection of SiC fiber for the fabrication of high performance SiC/SiC composites. In this study, unidirection and two dimension woven structures of SiC/SiC composites were prepared starting from Tyranno SA fiber. SiC matrix was obtained by nano-powder infiltration and transient eutectoid (NITE) process. Effect of microstructure and density on the sintering temperature in NITE-SiC/SiC composites are described and discussed with the fiber direction of unidirection and two dimension woven structures.

• 대한전자공학회논문지
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• 제26권11호
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• pp.1672-1678
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• 1989

Major problems preventing the device-quality GaAs/Si heterostructure are the lattice mismatch of about 4% and difference in thermal expansion coefficient by a factor of 2.64 between Si and GaAs. Ge is a good candidate for the buffer layer because its lattice parameter and thermal expansion coefficient are almost the same as those of GaAs. As a first step toward developing heterostructure such as GaAs/Ge/Si entirely by a home-built PAE (plasma-assisted epitaxy), Ge films have been deposited on p-type Si (100)substrate by the plasma assisted evaporation of solid Ge source. The characteristics of these Ge/Si heterostructure were determined by X-ray diffraction, SEM and Auge electron spectroscope. PAE system has been successfully applied to quality-good Ge layer on Si substrate at relatively low temperature. Furthermore, this system can remove the native oxide(SiO2) on Si substrate with in-situ cleaning procedure. Ge layer grown on Si substrate by PAE at substrate temperature of 450\ulcorner in hydrogen partial pressure of 10mTorr was expected with a good buffer layer for GaAs/Ge/Si heterostructure.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2007년도 하계학술대회 논문집 Vol.8
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• pp.333-334
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• 2007

This paper describes the characteristics of poly (polycrystalline) 3C-SiC grown on SiOz and AlN substrates, respectively. The crystalline quality of poly 3C-SiC was improved from resulting in decrease of FWHM (full width half maximum) of XRD by increasing the growth temperature. The minimum growth temperature of poly 3C-SiC was $1100^{\circ}C$. The surface chemical composition and the electron mobility of poly 3C-SiC grown on each substrate were investigated by XPS and Hall Effect, respectively. The chemical compositions of surface of poly 3C-SiC films grown on $SiO_2$ and AlN were not different. However, their electron mobilities were $7.65\;cm^2/V.s$ and $14.8\;cm^2/V.s$, respectively. Therefore, since the electron mobility of poly 3C-SiC films grown on AlN buffer layer was two times higher than that of 3C-SiC/$SiO_2$, a AlN film is a suitable material, as buffer layer, for the growth of poly 3C-SiC thin films with excellent properties for M/NEMS applications.

• 한국세라믹학회지
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• 제35권5호
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• pp.486-492
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• 1998

Silicon carbide (SiC) thin films were deposited on the porous silicon substrates by chemical vapour de-position(CVD) using MTS as a source material. The deposited films were ${\beta}$-SiC with poor crystallity con-firmed by XRD measurement. It was considered that the films showed the mixed characteistics of cry-stalline and amorphous SiC where amorphous SiC where amorphous SiC played a role of buffer layer in interface between as-dep films and Si substrate. The buffer layer reduced lattice mismatch to some extent the generally occurs when SiC films are deposited on Si. The low temperature (10K) PL (phtoluminescence) studies showed two broad bands with peaks at 600 and 720 for the films deposited at 1100$^{\circ}C$ The maximum PL peak of the crystalline SiC was observed at 600 nm and the amrophous SiC of 720 nm was also confirmed. PL peak due the amorphous SiC was smaller than that of the crystalline SiC, PL of porous Si might be disapperared due to densification during heat treatment.

• 한국표면공학회지
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• 제29권5호
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• pp.407-414
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• 1996

We have investigated the effects of H atoms on thin film growth processes and surface reactions. In the oxidation of Si, Si surfaces are passivated against the $O_2$ adsorption by terminating dangling bonds with H atoms. Moreover, the existence of Si-H bonds on Si(100) surfaces enhances the structural relaxation of Si-O-Si bonds due to a charge transfer from Si-Si back bonds. In the heteroepitaxial growth of a Si/Ge/Si(100) system, H atoms suppress the segregation of Ge atoms into Si overlayers since the exchange of Ge atoms with Si atoms bound with H must be accompanied with breaking of Si-H bonds. However, 3-dimensional island growth is also promoted by atomic H irradiation, which is considered to result from the suppression of surface migration of adsorbed reaction species and from the lowering of step energies by the H termination of dangling bonds.

• 한국반도체및디스플레이장비학회:학술대회논문집
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• 한국반도체및디스플레이장비학회 2006년도 춘계학술대회
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• pp.211-215
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• 2006

평면 광도파로 코어로 사용되는 SiON (Silicon oxynitride)과 클래딩으로 사용되는 $SiO_2$ (Silicon oxide)의 굴절률 차이가 2.5 %인 고굴절률차 평면 광도파로용 SiON 박막을 PECVD (plasma enhanced chemical vapor deposition)로 제작하였다. PECVD에 사용된 가스는 $SiH_4,\;NH_3,\;N_{2}O$이고, Si 기판의 $SiO_2$ 막은 100 nm이다. 가스의 비율에 따라 SiON 막의 굴절률은 633 nm의 파장에서 1.476에서 1.777까지 변화하였다. 코어로 사용되는 SiON의 두께는 $2.5{\mu}m$이고 클래딩과의 굴절률 차이는 2.5 %였다.

• 한국재료학회지
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• 제14권5호
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• pp.343-347
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• 2004

We investigated the growth feasibility of polycrystalline Si film on mica substrate for the transfer of the layer to a plastic substrate. The annealing temperature was limited up to $600^{\circ}C$ because of crack development in the mica substrate. Amorphous Si film was deposited on mica substrate by PECVD and was crystallized by furnace annealing. During the annealing, bubbles were formed at the Si/mica interface. The bubble formation was avoided by the Ar-plasma treatment before amorphous Si deposition. A uniform and clean polycrystalline Si film was obtained by coating $NiCl_2$ on the amorphous Si film and annealing at $500^{\circ}C$ for 10 h. The conventional Si lithography was possible on the mica substrate and the devices fabricated on the substrate could be transferred to a plastic substrate.

• E2M - 전기 전자와 첨단 소재
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• 제9권1호
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• pp.30-37
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• 1996

Previously, crystallization of a-Si:H films on glass substrates were limited to anneal temperature below 600.deg. C, over 10 hours to avoid glass shrinkage. Our study indicates that the crystallization is strongly influenced by anneal temperature and weakly affected by anneal duration time. Because of the high temperature process and nonconducting substrate requirements for poly-Si TFTs, the employed substrates were limited to quartz, sapphire, and oxidized Si wafer. We report on poly-Si TFT's using high temperature anneal on a Si:H/Mo structures. The metal Mo substrate was stable enough to allow 1000.deg. C anneal. A novel TFT fabrication was achieved by using part of the Mo substrate as drain and source ohmic contact electrode. The as-grown a-Si:H TFT was compared to anneal treated poly-Si TFT'S. Defect induced trap states of TFT's were examined using the thermally stimulated current (TSC) method. In some case, the poly-Si grain boundaries were passivated by hydrogen. A-SI:H and poly-Si TFT characteristics were investigated using an inverted staggered type TFT. The poly -Si films were achieved by various anneal techniques; isothermal, RTA, and excimer laser anneal. The TFT on as grown a-Si:H exhibited a low field effect mobility, transconductance, and high gate threshold voltage. Some films were annealed at temperatures from 200 to >$1000^{\circ}C$ The TFT on poly-Si showed an improved $I_on$$I_off$ ratio of $10_6$, reduced gate threshold voltage, and increased field effect mobility by three orders. Inverter operation was examined to verify logic circuit application using the poly Si TFTs.